Dma Support - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

After the address matching IAAS bit is set, an interrupt is sent at the end of address

matching to wake the core. The IAAS bit must be cleared after the clock recovery.

After the system recovers and is in Run mode, restart the I2C

module if it is needed to transfer packets. To avoid I2C transfer

problems resulting from the situation, firmware should prevent

the MCU execution of a STOP instruction when the I2C

module is in the middle of a transfer unless the Stop mode

holdoff feature is used during this period (set FLT[SHEN] to 1).

After I2C address matching wake-up, the master must wait a

time long enough for the slave ISR to finish running and resend

start or repeat start signals.

For the SRW bit to function properly, it only supports Address

+Write to wake up by I2C address matching. Before entering

the next low power mode, Address+Write must be sent to

change the SRW status.

36.5.9 DMA support

If the DMAEN bit is cleared and the IICIE bit is set, an interrupt condition generates an

interrupt request.

If the DMAEN bit is set and the IICIE bit is set, an interrupt condition generates a DMA

request instead. DMA requests are generated by the transfer complete flag (TCF).

If the DMAEN bit is set, only the TCF initiates a DMA request. All other events generate

CPU interrupts.

Before the last byte of master receive mode, TXAK must be set

to send a NACK after the last byte's transfer. Therefore, the

DMA must be disabled before the last byte's transfer.

In 10-bit address mode transmission, the addresses to send

occupy 2–3 bytes. During this transfer period, the DMA must

be disabled because the C1 register is written to send a repeat

start or to change the transfer direction.

Freescale Semiconductor, Inc.

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 36 Inter-Integrated Circuit (I2C)