Table of Contents
Advertisement
SWD status and control registers
Table 9-3. MDM-AP Control register assignments (continued)
Bit
Name
3
System Reset Request
4
Core Hold Reset
5
VLLSx Debug Request
(VLLDBGREQ)
6
VLLSx Debug Acknowledge
(VLLDBGACK)
7
LLS, VLLSx Status Acknowledge
8 –
Reserved for future use
31
1. Command available in secure mode
106
1
Secure
If the core is in a Stop or Wait mode, this bit can be used to wake the
core and transition to a halted state.
Y
Set to force a system reset. The system remains held in reset until this
bit is cleared.
N
Configuration bit to control core operation at the end of system reset
sequencing.
0 Normal operation: Release the core from reset along with the rest of
the system at the end of system reset sequencing.
1 Suspend operation: Hold the core in reset at the end of reset
sequencing. Once the system enters this suspended state, clearing
this control bit immediately releases the core from reset and CPU
operation begins.
N
Set to configure the system to be held in reset after the next recovery
from a VLLSx mode. This bit is ignored on a VLLS wakeup via the
Reset pin. During a VLLS wakeup via the Reset pin, the system can be
held in reset by holding the reset pin asserted allowing the debugger to
reinitialize the debug modules.
This bit holds the system in reset when VLLSx modes are exited to
allow the debugger time to re-initialize debug IP before the debug
session continues.
The Mode Controller captures this bit logic on entry to VLLSx modes.
Upon exit from VLLSx modes, the Mode Controller will hold the system
in reset until VLLDBGACK is asserted.
VLLDBGREQ clears automatically due to the POR reset generated as
part of the VLLSx recovery.
N
Set to release a system being held in reset following a VLLSx recovery
This bit is used by the debugger to release the system reset when it is
being held on VLLSx mode exit. The debugger re-initializes all debug
IP and then assert this control bit to allow the Mode Controller to
release the system from reset and allow CPU operation to begin.
VLLDBGACK is cleared by the debugger or can be left set because it
clears automatically due to the POR reset generated as part of the
next VLLSx recovery.
N
Set this bit to acknowledge the DAP LLS and VLLS Status bits have
been read. This acknowledge automatically clears the status bits.
This bit is used by the debugger to clear the sticky LLS and VLLSx
mode entry status bits. This bit is asserted and cleared by the
debugger.
N
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
Freescale Semiconductor, Inc.
Advertisement
Table of Contents
