Input Capture Mode - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Functional description
• When (CSOT = 1), the counter will not start incrementing until a rising edge is
detected on the trigger input.
• When (CSOO= 1), the counter will stop incrementing whenever the TOF flag is set.
The counter does not increment again unless it is disabled, or if CSOT = 1 and a
rising edge is detected on the trigger input.
• When (CROT= 1), the counter will reset to zero as if an overflow occurred whenever
a rising edge is detected on the trigger input.
• When (CPOT = 1), the counter will pause incrementing whenever the trigger input is
asserted. The counter will continue incrementing when the trigger input negates.
The polarity of the external input trigger can be configured by the TRGPOL register bit.
When an internal trigger source is selected, the trigger input is selected from one or more
channel input capture events. The input capture filters are used with the internal trigger
sources and the POLn bits can be used to invert the polarity of the input channels. Note
that following restrictions apply with input capture channel sources.
• When (CSOT = 1), the counter will only start incrementing on a rising edge on the
channel input, provided ELSnA = 1.
• When (CROT= 1), the counter will reset to zero on either edge of the channel input,
as configured by ELSnB:ELSnA.
• When (CPOT = 1), the counter will pause incrementing whenever the channel input
is asserted.

29.5.4 Input Capture Mode

The input capture mode is selected when (CPWMS = 0), (MSnB:MSnA = 0:0), and
(ELSnB:ELSnA ≠ 0:0).
When a selected edge occurs on the channel input, the current value of the TPM counter
is captured into the CnV register, at the same time the CHnF bit is set and the channel
interrupt is generated if enabled by CHnIE = 1 (see the following figure).
When a channel is configured for input capture, the TPM_CHn pin is an edge-sensitive
input. ELSnB:ELSnA control bits determine which edge, falling or rising, triggers input-
capture event. Note that the maximum frequency for the channel input signal to be
detected correctly is counter clock divided by 4, which is required to meet Nyquist
criteria for signal sampling.
Writes to the CnV register are ignored in input capture mode.
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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.