Features - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Introduction
The following figure is a simplified block diagram of the 4-channel DMA controller.
Slave
Peripheral Bus
Requests
SysBus Interface
Data Path
Read Data Bus Write Data Bus
The terms peripheral request and DREQ refer to a DMA request from one of the on-chip
peripherals or package pins. The DMA provides hardware handshake signals: either a
DMA acknowledge (DACK) or a done indicator back to the peripheral.

21.1.2 Features

The DMA controller module features:
• Four independently programmable DMA controller channels
• Dual-address transfers via 32-bit master connection to the system bus
• Data transfers in 8-, 16-, or 32-bit blocks
• Continuous-mode or cycle-steal transfers from software or peripheral initiation
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DREQ0 DREQ1
DACK1
DACK0
Channel 0 Channel 1
SAR0 SAR1
DAR0 DAR1
DSR0 DSR1
BCR0 BCR1
DCR0 DCR1
Channel
Channel
Enables
MUX
Control
Data Path
Control
Figure 21-1. 4-Channel DMA Block Diagram
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
DREQ2 DREQ3
DACK3
DACK2
Channel 2 Channel 3
SAR2 SAR3
DAR2 DAR3
DSR2 DSR3
BCR2 BCR3
DCR2 DCR3
Channel
Attributes
System Bus Address
MUX
System Bus Size
Current Master Attributes
Arbitraton/
Control
Interrupts
SysBus Interface
Addr + Attr
Registered Addr
Phase Bus Signals
Freescale Semiconductor, Inc.