System Memory Map - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Also, it retains contents during low-voltage detect (LVD) events and is only reset during
a power-on reset.

4.5 System memory map

The table found here shows the high-level device memory map.
System 32-bit address range
0x0000_0000–0x07FF_FFFF
0x0800_0000–0x1BFF_FFFF
0x1C00_0000 – 0x1C00_3FFF
0x1C00_4000 – 0x1FFF_DFFF
0x1FFF_E000–0x1FFF_FFFF
0x2000_0000–0x2000_5FFF
0x2000_6000–0x3FFF_FFFF
0x4000_0000–0x4007_FFFF
0x4008_0000–0x400F_EFFF
0x400F_F000–0x400F_FFFF
0x4010_0000–0x43FF_FFFF
0x4400_0000–0x5FFF_FFFF
0x6000_0000–0xDFFF_FFFF
0xE000_0000–0xE00F_FFFF
0xE010_0000–0xEFFF_FFFF
0xF000_0000–0xF000_0FFF
0xF000_1000–0xF000_1FFF
0xF000_2000–0xF000_2FFF
0xF000_3000–0xF000_3FFF
0xF000_4000–0xF7FF_FFFF
0xF800_0000–0xFFFF_FFFF
1. The program flash always begins at 0x0000_0000 but the end of implemented flash varies depending on the amount of
flash implemented for a particular device. See
2. This range varies depending on SRAM sizes. See
3. Includes BME operations to GPIO at slot 15 (based at 0x4000_F000).
Freescale Semiconductor, Inc.
Table 4-3. System memory map
1
Program flash and read-only data
(Includes exception vectors in first 192 bytes)
Reserved
Boot ROM
Reserved
, 2
SRAM_L: Lower SRAM
2
SRAM_U: Upper SRAM
Reserved
AIPS Peripherals
Reserved
General-purpose input/output (GPIO)
Reserved
Bit Manipulation Engine (BME) access to AIPS Peripherals for
3
slots 0-127
Reserved
Private Peripherals
Reserved
Micro Trace Buffer (MTB) registers
MTB Data Watchpoint and Trace (MTBDWT) registers
ROM table
Miscellaneous Control Module (MCM)
Reserved
IOPORT: GPIO (single cycle)
Flash memory
SRAM sizes
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Destination slave
for details.
for details.
Chapter 4 Memory Map
Access
All masters
—
All masters
—
All masters
All masters
–
Cortex-M0+ core &
DMA
–
Cortex-M0+ core &
DMA
–
Cortex-M0+ core
–
Cortex-M0+ core
–
Cortex-M0+ core
Cortex-M0+ core
Cortex-M0+ core
Cortex-M0+ core
–
Cortex-M0+ core
59