Boot Sequence - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table 6-2. Flash Option Register (FTFA_FOPT) definition
Bit Field
Num
1. Refer to Clock divider values after reset

6.3.3 Boot sequence

At power up, the on-chip regulator holds the system in a POR state until the input supply
exceeds the POR threshold. The system continues to be held in this static state until the
internally regulated supplies have reached a safe operating voltage as determined by the
LVD. The Reset Controller logic then controls a sequence to exit reset.
1. A system reset is held on internal logic, the RESET pin is driven out low, and the
MCG-Lite is enabled in its default clocking mode.
2. Required clocks are enabled (system clock, flash clock, and any bus clocks that do
not have clock gate control reset to disabled).
3. The system reset on internal logic continues to be held, but the Flash Controller is
released from reset and begins initialization operation while the Reset Control logic
continues to drive the RESET pin out low.
4. Early in reset sequencing, the NVM option byte is read and stored to the FOPT
register of the Flash Memory module (FTFA_FOPT). If the bits associated with
FTFA_FOPT[LPBOOT] are programmed for an alternate clock divider reset value,
the system/core clock is switched to a slower clock speed. If
FTFA_FOPT[FAST_INIT] is programmed clear, the flash initialization switches to
slower clock resulting longer recovery times.
5. When flash Initialization completes, the RESET pin is released. If RESET continues
to be asserted (an indication of a slow rise time on the RESET pin or external drive
in low), the system continues to be held in reset. Once the RESET pin is detected
high, the core clock is enabled and the system is released from reset.
6. When the system exits reset, the processor sets up the stack, program counter (PC),
and link register (LR). The processor reads the start SP (SP_main) from vector-table
offset 0. The core reads the start PC from vector-table offset 4. LR is set to
0xFFFF_FFFF. The next sequence of events depends on the NMI/BOOTCFG0 input
Freescale Semiconductor, Inc.
(continued)
Value
00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8). Device is configured
for VLPR mode on exit from reset.
01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4). Device is configured
for VLPR mode on exit from reset.
10 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2). Device is configured
for RUN mode on exit from reset.
11 Core and system clock divider (OUTDIV1) is 0x0 (divide by 1). Device is configured
for RUN mode on exit from reset.
and RCM_FM, RCM_MR in the
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 6 Reset and Boot
Definition
Reset Control Module (RCM) for details.
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