Spi Fifo Mode - NXP Semiconductors MKL27Z128VFM4 Reference Manual

If C1[CPHA] is set, even numbered edges on the SPSCK input cause the data at the serial
data input pin to be latched. Odd numbered edges cause the value previously latched
from the serial data input pin to shift into the LSB or MSB of the SPI shift register,
depending on C1[LSBFE].
When C1[CPHA] is set, the first edge is used to get the first data bit onto the serial data
output pin. When C1[CPHA] is clear and the SS input is low (slave selected), the first bit
of the SPI data is driven out of the serial data output pin. After the eighth (SPIMODE =
0) or sixteenth (SPIMODE = 1) shift, the transfer is considered complete and the received
data is transferred into the SPI Data register. To indicate transfer is complete, the SPRF
flag in the SPI Status Register is set.
A change of the bits FIFOMODE,SPIMODE, C2[BIDIROE]
with C2[SPC0] set, C1[CPOL], C1[CPHA], C1[SSOE],
C1[LSBFE], C2[MODFEN], and C2[SPC0] in slave mode will
corrupt a transmission in progress and must be avoided.

35.5.4 SPI FIFO Mode

When the FIFO feature is supported: The SPI works in FIFO mode when the
C3[FIFOMODE] bit is set. When the module is in FIFO mode, the SPI RX buffer and
SPI TX buffer are replaced by an 8-byte-deep FIFO, as the following figures show.
Figure 35-4. SPIH:L read side structural overview in FIFO mode
Freescale Semiconductor, Inc.
Read Access
SPI_REG_BLOCK
spidh:l_rx_reg
FIFO Ctrlr
SPI_CORE_SHFR
Load
Control
shfr_rx_reg
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 35 Serial Peripheral Interface (SPI)
Note
IPBus (ips_rdata[7:0])
SPI Data Register
FIFO depth = 8 bytes
RX- FIFO
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