Adc Minus-Side General Calibration Value Register (Adcx_Clm0); Functional Description - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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23.4.24 ADC Minus-Side General Calibration Value Register

For more information, see CLMD register description.

Address: 4003_B000h base + 6Ch offset = 4003_B06Ch

This field is reserved.

This read-only field is reserved and always has the value 0.

Calibration Value

The ADC module is disabled during reset, in Low-Power Stop mode, or when

SC1n[ADCH] are all high; see the power management information for details. The

module is idle when a conversion has completed and another conversion has not been

initiated. When it is idle and the asynchronous clock output enable is disabled, or

CFG2[ADACKEN]= 0, the module is in its lowest power state. The ADC can perform an

analog-to-digital conversion on any of the software selectable channels. All modes

perform conversion by a successive approximation algorithm.

To meet accuracy specifications, the ADC module must be calibrated using the on-chip

calibration function.

Calibration function

When the conversion is completed, the result is placed in the Rn data registers. The

respective SC1n[COCO] is then set and an interrupt is generated if the respective

conversion complete interrupt has been enabled, or, when SC1n[AIEN]=1.

The ADC module has the capability of automatically comparing the result of a

conversion with the contents of the CV1 and CV2 registers. The compare function is

enabled by setting SC2[ACFE] and operates in any of the conversion modes and

configurations.

Freescale Semiconductor, Inc.

ADCx_CLM0 field descriptions

for details on how to perform calibration.

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 23 Analog-to-Digital Converter (ADC)