Introduction; Cmp Features - NXP Semiconductors MKL27Z128VFM4 Reference Manual

• In Time Counter mode with prescaler enabled, the delay is 1/2 Prescaler output
period.
• In Time Counter mode with prescaler bypassed, the delay is 1/2 Prescaler clock
period.
The delay between the first signal from LPTMR and the second signal from LPTMR
must be greater than the analog comparator initialization delay as defined in the device
datasheet.

24.2 Introduction

The comparator (CMP) module provides a circuit for comparing two analog input
voltages. The comparator circuit is designed to operate across the full range of the supply
voltage, known as rail-to-rail operation.
The Analog MUX (ANMUX) provides a circuit for selecting an analog input signal from
eight channels. One signal is provided by the 6-bit digital-to-analog converter (DAC).
The mux circuit is designed to operate across the full range of the supply voltage.
The 6-bit DAC is 64-tap resistor ladder network which provides a selectable voltage
reference for applications where voltage reference is needed. The 64-tap resistor ladder
network divides the supply reference V
input selects the output voltage level, which varies from V
from two voltage sources, V
as an on-chip internal signal only and is not available externally to a pin.

24.2.1 CMP features

The CMP has the following features:
• Operational over the entire supply range
• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the
comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as:
Freescale Semiconductor, Inc.
into 64 voltage levels. A 6-bit digital signal
in
and V . The 6-bit DAC from a comparator is available
in1 in2
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 24 Comparator (CMP)
to V /64. V can be selected
in in in
393