NXP Semiconductors KE1xF Series Reference Manual

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Kinetis KE1xF Sub-Family Reference

Manual

Supports: MKE1xF512VLL16, MKE1xF512VLH16, MKE1xF256VLL16,

MKE1xF256VLH16

Document Number: KE1xFP100M168SF0RM

Rev. 4, 06/2019

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Summary of Contents for NXP Semiconductors KE1xF Series

Page 1 Kinetis KE1xF Sub-Family Reference Manual Supports: MKE1xF512VLL16, MKE1xF512VLH16, MKE1xF256VLL16, MKE1xF256VLH16 Document Number: KE1xFP100M168SF0RM Rev. 4, 06/2019...
Page 2 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 3: Table Of Contents
Chapter 3 Core Overview ARM Cortex-M4 ................................57 Core Buses and Interfaces.............................58 Core Component Configuration............................59 SysTick Clock Configuration............................59 Chapter 4 Interrupts Introduction...................................61 NVIC configuration..............................61 4.2.1 Interrupt priority levels..........................61 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 4 Miscellaneous Control register (SIM_MISCTRL)..................85 Chapter 6 Miscellaneous Control Module (MCM) Introduction...................................87 6.1.1 Features................................ 87 Memory map/register descriptions..........................87 6.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..............88 6.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............89 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 5 7.1.1 Instantiation Information..........................109 Introduction...................................110 7.2.1 Features................................ 110 Memory Map / Register Definition..........................110 Functional Description..............................110 7.4.1 General operation............................111 7.4.2 Arbitration..............................111 Initialization/application information........................... 113 Chapter 8 Memory Protection Unit (MPU) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 6 MPU Access Violation Indications......................135 8.8.2 Reset Values for RGD0 Registers........................136 8.8.3 Write Access Restrictions for RGD0 Registers................... 136 Chapter 9 Peripheral Bridge (AIPS-Lite) Chip-specific information for this module........................139 9.1.1 Peripheral slot assignment........................... 139 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 7 CMP Window/Sample Input ........................208 10.5.3 FTM Fault Detection Input / Hardware Triggers and Synchronization............208 Chapter 11 Direct Memory Access Multiplexer (DMAMUX) 11.1 Chip-specific information for this module........................209 11.1.1 Instantiation Information..........................209 11.2 Introduction...................................212 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 8 TCD structure...............................227 12.3.4 Reserved memory and bit fields........................228 12.3.5 Control Register (DMA_CR)........................239 12.3.6 Error Status Register (DMA_ES)........................ 242 12.3.7 Enable Request Register (DMA_ERQ)....................... 244 12.3.8 Enable Error Interrupt Register (DMA_EEI)....................246 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 9 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_CITER_ELINKNO)......................275 12.3.33 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..276 12.3.34 TCD Control and Status (DMA_TCDn_CSR).................... 277 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 10 Flash memory types............................. 309 13.2.2 Flash Memory Sizes.............................309 13.3 SRAM memory................................310 13.3.1 SRAM sizes..............................310 13.3.2 SRAM retention in low power modes......................310 13.3.3 SRAM accesses............................310 13.3.4 SRAM arbitration and priority control......................311 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 11 14.4.4 Cache Control.............................. 337 Chapter 15 Miscellaneous System Control Module (MSCM) 15.1 Overview..................................343 15.2 Chip Configuration and Boot............................343 15.3 MSCM Memory Map/Register Definition........................344 15.3.1 CPU Configuration Memory Map and Registers..................344 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 12 Chip-specific Information for this Module........................361 17.2 Introduction...................................361 17.2.1 Features................................ 362 17.2.2 Block diagram.............................. 364 17.2.3 Glossary............................... 364 17.3 External signal description............................367 17.4 Memory map and registers............................367 17.4.1 Flash configuration field description......................367 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 13 High-level clocking diagram............................436 18.3 Clock definitions................................436 18.4 Typical Clock Configuration............................437 18.4.1 Default start-up clock...........................438 18.4.2 VLPR mode clocking...........................439 18.5 Clock Gating................................. 439 18.6 Module clocks................................439 18.6.1 LPO clock distribution..........................441 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 14 System OSC Divide Register (SCG_SOSCDIV)..................464 19.3.10 System Oscillator Configuration Register (SCG_SOSCCFG)..............465 19.3.11 Slow IRC Control Status Register (SCG_SIRCCSR)..................467 19.3.12 Slow IRC Divide Register (SCG_SIRCDIV)....................468 19.3.13 Slow IRC Configuration Register (SCG_SIRCCFG).................. 469 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 15 Functional Description..............................488 20.6 Reset Overview................................489 20.7 Interrupts..................................489 Chapter 21 Peripheral Clock Controller (PCC) 21.1 Chip-specific information for this module........................491 21.1.1 Information of PCC on this device......................491 21.2 Introduction...................................491 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 16 23.3.2 The Kinetis Bootloader Configuration Area (BCA)..................566 23.3.3 Start-up Process............................568 23.3.4 Clock Configuration.............................570 23.3.5 Bootloader Entry Point / API Tree.......................571 23.3.6 Bootloader Protocol............................. 572 23.3.7 Bootloader Packet Types..........................577 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 17 Version ID Register (RCM_VERID)......................632 24.3.2 Parameter Register (RCM_PARAM)......................634 24.3.3 System Reset Status Register (RCM_SRS)....................636 24.3.4 Reset Pin Control register (RCM_RPC)...................... 639 24.3.5 Mode Register (RCM_MR)......................... 640 24.3.6 Force Mode Register (RCM_FM)........................641 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 18 Memory map and register descriptions.........................665 26.4.1 SMC Version ID Register (SMC_VERID)....................666 26.4.2 SMC Parameter Register (SMC_PARAM)....................667 26.4.3 Power Mode Protection register (SMC_PMPROT)..................668 26.4.4 Power Mode Control register (SMC_PMCTRL)..................669 26.4.5 Stop Control Register (SMC_STOPCTRL)....................671 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 19 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)............687 27.6.3 Regulator Status and Control Register (PMC_REGSC)................688 27.6.4 Low Power Oscillator Trim Register (PMC_LPOTRIM)................689 Chapter 28 Security 28.1 Introduction...................................691 28.2 Flash security feature summary............................ 691 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 20 The EWM_out Signal..........................701 29.4.2 The EWM_in Signal............................ 702 29.4.3 EWM Counter.............................. 703 29.4.4 EWM Compare Registers..........................703 29.4.5 EWM Refresh Mechanism...........................703 29.4.6 EWM Interrupt............................. 704 29.4.7 Counter clock prescaler..........................704 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 21 Backup reset..............................719 30.4.6 Functionality in debug and low-power modes..................... 720 30.4.7 Fast testing of the watchdog.........................720 30.5 Application Information..............................721 30.5.1 Disable Watchdog............................722 30.5.2 Configure Watchdog............................ 722 30.5.3 Refreshing the Watchdog..........................723 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 22 CM4 ROM table................................739 32.3 The Debug Port................................740 32.3.1 JTAG-to-SWD change sequence......................... 740 32.4 Debug Port Pin Descriptions............................741 32.5 System TAP connection..............................741 32.5.1 IR Codes...............................741 32.6 JTAG status and control registers..........................742 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 23 TMS—Test mode select..........................754 33.3 Register description..............................754 33.3.1 Instruction register............................754 33.3.2 Bypass register............................. 755 33.3.3 Device identification register........................755 33.3.4 Boundary scan register..........................756 33.4 Functional description..............................756 33.4.1 JTAGC reset configuration.......................... 756 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 24 35.1 Chip-specific information for this module........................777 35.1.1 I/O pin structure............................777 35.1.2 Port control and interrupt module features....................778 35.1.3 Application-related Information........................778 35.2 Introduction...................................779 35.3 Overview..................................779 35.3.1 Features................................ 779 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 25 Memory map and register definition..........................801 36.3.1 Port Data Output Register (GPIOx_PDOR)....................803 36.3.2 Port Set Output Register (GPIOx_PSOR)....................803 36.3.3 Port Clear Output Register (GPIOx_PCOR)....................804 36.3.4 Port Toggle Output Register (GPIOx_PTOR)..................... 804 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 26 ADC Data Result Registers (ADCx_Rn)..................... 833 37.4.5 Compare Value Registers (ADCx_CVn)..................... 834 37.4.6 Status and Control Register 2 (ADCx_SC2)....................835 37.4.7 Status and Control Register 3 (ADCx_SC3)....................837 37.4.8 BASE Offset Register (ADCx_BASE_OFS)....................838 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 27 Voltage reference selection.......................... 850 37.5.3 Hardware trigger and channel selects......................850 37.5.4 Conversion control............................851 37.5.5 Automatic compare function........................855 37.5.6 Calibration function............................. 856 37.5.7 User-defined offset function........................857 37.5.8 MCU wait mode operation...........................858 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 28 CMP block diagram..............................874 38.6 CMP pin descriptions..............................875 38.6.1 External pins..............................875 38.7 CMP functional modes..............................876 38.7.1 Disabled mode (# 1)............................. 878 38.7.2 Continuous mode (#s 2A & 2B)........................878 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 29 Zero Crossing Detection..........................902 38.14.2 Window Mode..............................903 38.14.3 Round Robin Mode............................904 Chapter 39 12-bit Digital-to-Analog Converter (DAC) 39.1 Chip-specific information for this module........................907 39.1.1 Instantiation information..........................907 39.1.2 DAC Clocking Information......................... 907 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 30 PDB Module Interconnections........................922 40.2 Introduction...................................926 40.2.1 Features................................ 926 40.2.2 Implementation............................927 40.2.3 Back-to-back acknowledgment connections....................927 40.2.4 DAC External Trigger Input Connections....................928 40.2.5 Block diagram.............................. 928 40.2.6 Modes of operation............................930 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 31 PDB pre-trigger and trigger outputs......................947 40.5.2 PDB trigger input source selection......................949 40.5.3 DAC interval trigger outputs........................949 40.5.4 Pulse-Out's..............................950 40.5.5 Updating the delay registers.........................951 40.5.6 Interrupts..............................953 40.5.7 DMA................................953 40.6 Application information..............................953 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 32 Counter Initial Value (FTMx_CNTIN)......................981 41.4.9 Capture And Compare Status (FTMx_STATUS)..................982 41.4.10 Features Mode Selection (FTMx_MODE)....................984 41.4.11 Synchronization (FTMx_SYNC)......................... 986 41.4.12 Initial State For Channels Output (FTMx_OUTINIT).................988 41.4.13 Output Mask (FTMx_OUTMASK)......................990 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 33 41.5.6 Output Compare mode..........................1034 41.5.7 Edge-Aligned PWM (EPWM) mode......................1036 41.5.8 Center-Aligned PWM (CPWM) mode......................1038 41.5.9 Combine mode............................. 1040 41.5.10 Complementary Mode..........................1047 41.5.11 Registers updated from write buffers......................1048 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 34 Output Logic..............................1103 41.5.33 Dithering..............................1104 41.6 Reset overview................................1113 41.7 FTM Interrupts................................1115 41.7.1 Timer Overflow Interrupt..........................1115 41.7.2 Reload Point Interrupt..........................1115 41.7.3 Channel (n) Interrupt............................1115 41.7.4 Fault Interrupt.............................. 1115 41.8 Initialization Procedure..............................1116 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 35 42.4.7 Clear Timer Enable Register (LPITx_CLRTEN)..................1132 42.4.8 Timer Value Register (LPITx_TVALn)...................... 1133 42.4.9 Current Timer Value (LPITx_CVALn)....................... 1134 42.4.10 Timer Control Register (LPITx_TCTRLn)....................1135 42.5 Functional description..............................1136 42.5.1 Initialization..............................1136 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 36 Pulse Width Timer Negative Pulse Width Register: High (PWT_NPH).............1152 43.4.6 Pulse Width Timer Negative Pulse Width Register: Low (PWT_NPL)............1152 43.4.7 Pulse Width Timer Counter Register: High (PWT_CNTH)................ 1153 43.4.8 Pulse Width Timer Counter Register: Low (PWT_CNTL)................. 1153 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 37 Low Power Timer Prescale Register (LPTMRx_PSR)................1170 44.4.3 Low Power Timer Compare Register (LPTMRx_CMR)................1172 44.4.4 Low Power Timer Counter Register (LPTMRx_CNR)................1172 44.5 Functional description..............................1172 44.5.1 LPTMR power and reset..........................1173 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 38 RTC Time Compensation Register (RTC_TCR)..................1184 45.3.5 RTC Control Register (RTC_CR)........................1186 45.3.6 RTC Status Register (RTC_SR)........................1188 45.3.7 RTC Lock Register (RTC_LR)........................1189 45.3.8 RTC Interrupt Enable Register (RTC_IER)....................1190 45.3.9 RTC Write Access Register (RTC_WAR)....................1192 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 39 Features................................ 1203 46.2.3 Block Diagram............................. 1204 46.2.4 Modes of operation............................1204 46.2.5 Signal Descriptions............................1205 46.3 Memory Map and Registers............................1206 46.3.1 Version ID Register (LPSPIx_VERID)....................... 1207 46.3.2 Parameter Register (LPSPIx_PARAM)....................... 1208 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 40 Low Power Inter-Integrated Circuit (LPI2C) 47.1 Chip-specific information for this module........................1235 47.1.1 Instantiation Information..........................1235 47.1.2 Module Clocking Information for LPUART, LPSPI, LPI2C, FlexIO and LPIT.........1235 47.1.3 Inter-connectivity Information........................1236 47.2 Introduction...................................1237 47.2.1 Overview..............................1237 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 41 Slave Interrupt Enable Register (LPI2Cx_SIER)..................1264 47.3.21 Slave DMA Enable Register (LPI2Cx_SDER)....................1265 47.3.22 Slave Configuration Register 1 (LPI2Cx_SCFGR1)................... 1266 47.3.23 Slave Configuration Register 2 (LPI2Cx_SCFGR2)................... 1268 47.3.24 Slave Address Match Register (LPI2Cx_SAMR)..................1269 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 42 48.3 Register definition.................................1293 48.3.1 LPUART Register Descriptions........................1293 48.4 Functional description..............................1317 48.4.1 Baud rate generation............................ 1317 48.4.2 Transmitter functional description....................... 1318 48.4.3 Receiver functional description........................1321 48.4.4 Additional LPUART functions........................1328 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 43 Timer Interrupt Enable Register (FLEXIO_TIMIEN).................1346 49.3.11 Shifter Status DMA Enable (FLEXIO_SHIFTSDEN)................1347 49.3.12 Shifter Control N Register (FLEXIO_SHIFTCTLn)...................1347 49.3.13 Shifter Configuration N Register (FLEXIO_SHIFTCFGn)................ 1349 49.3.14 Shifter Buffer N Register (FLEXIO_SHIFTBUFn)..................1350 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 44 Chip-specific information for this module........................1381 50.1.1 Instantiation Information..........................1381 50.1.2 FlexCAN Clocking Information........................1381 50.1.3 Inter-connectivity Information........................1382 50.2 Introduction...................................1382 50.2.1 Overview..............................1383 50.2.2 FlexCAN module features........................... 1384 50.2.3 Modes of operation............................1386 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 45 Rx Individual Mask Registers (CANx_RXIMRn)..................1424 50.4.53 Message buffer structure..........................1425 50.4.54 Rx FIFO structure............................1431 50.5 Functional description..............................1433 50.5.1 Transmit process............................1434 50.5.2 Arbitration process............................1435 50.5.3 Receive process............................1438 50.5.4 Matching process............................1441 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 46 Bus interface..............................1467 50.6 Initialization/application information........................... 1468 50.6.1 FlexCAN initialization sequence......................... 1468 50.7 Usage Guide..................................1470 50.7.1 FlexCAN Interrupts............................1470 50.7.2 FlexCAN Operation in Low Power Modes....................1470 50.7.3 FlexCAN Doze Mode..........................1470 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 47: About This Manual
• Chip-specific: The first section, Chip-specific [module name] information, includes the number of module instances on the chip and possible implementation differences between the module instances, such as differences in FIFO depths or the number of Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 48: Example: Chip-Specific Information That Supersedes Content In The Same Chapter
• LIN Specification Package Revision 1.3; December 12, 2002 • LIN Specification Package Revision 2.0; September 23, 2003 Sample Reference Manual Figure 1-1. Example: chapter chip-specific information and general module information Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 49: Example: Chip-Specific Information That Refers To A Different Chapter
1.3.2 Example: chip-specific information that refers to a different chapter The chip-specific information below refers to another chapter's chip-specific information. In this case, read both sets of chip-specific information before reading further in the chapter. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 50: Register Descriptions
• The page number on which each register is described • Register figures • Field-description tables • Associated text The register figures show the field structure using the conventions in the following figure. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 51: Conventions
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 52: Special Terms
• Consider undefined locations in memory to be reserved. Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 53: Introduction
-M4 MCUs and product family. It also presents high-level descriptions of the modules available on the device covered by this document. 2.2 Block Diagram The following figure shows a top-level block diagram of the MCU superset device. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 54: Module Functional Categories
Figure 2-1. MCU block diagram 2.3 Module Functional Categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 55 Communication interfaces • FlexCAN • Low-power Serial peripheral interface (LPSPI) • Low-power Inter-integrated circuit (LPI • Low-power UART (LPUART) • FlexIO Human-machine interfaces (HMI) • General purpose input/output controller (GPIO) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 56 Module Functional Categories Table 2-1. Module functional categories Module category Description • High drive I/O pins, see properties. • Digital filters, see "Ports summary" table in Port control and interrupt module features. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 57: Core Overview
• Flash Patch and Breakpoint Unit (FPB) • 24-bit system tick timer (SysTick) The detailed architecture and programming model of Cortex-M4 processor are discussed in the following documents from ARM. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 58: Core Buses And Interfaces
Debug SLEEPDEEP Instruction Data Trace port (serial wire or multi-pin) TPIU AWIC Private Peripheral Bus (internal) Table I-Code bus Code bus Matrix D-Code bus JTAG System bus SWJ-DP AHB-AP MDM-AP Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 59: Core Component Configuration
SysTick Calibration Value Register (SYST_CALIB) is always zero. • The NOREF bit in SysTick Calibration Value Register (SYST_CALIB) is always set, implying that CORE_CLK is the only available source of reference timing. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 60 SysTick Clock Configuration Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 61: Interrupts
ARM Cortex-M4 Processor Technical Reference Manual 4.2 NVIC configuration The NVIC supports configurable interrupt number and level of priority. The following sections speficy the exact priority level and interrupt vectors implemented on this device. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 62: Non-Maskable Interrupt
MemManage Fault 0x0000_0014 – – – ARM core Bus Fault 0x0000_0018 – – – ARM core Usage Fault 0x0000_001C – – – — — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 63 Flash memory Double bit fault detect interrupt 0x0000_0098 WDOG or EWM Both watchdog modules share this interrupt. 0x0000_009C — — 0x0000_00A0 — 0x0000_00A4 — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 64 SCG or RCM — 0x0000_0128 Low Power Timer — 0x0000_012C Port control module Pin detect (Port A) 0x0000_0130 Port control module Pin detect (Port B) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 65 3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 4. This interrupt can only be pended or cleared via the NVIC registers. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 66: Determining The Bitfield And Register Location For Configuring A Particular Interrupt
NVIC_IPR14 bitfield range is 20-23 Therefore, the following bitfield locations are used to configure the LPTMR interrupts: • NVIC_ISER1[26] • NVIC_ICER1[26] • NVIC_ISPR1[26] • NVIC_ICPR1[26] • NVIC_IABR1[26] • NVIC_IPR14[23:20] Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 67: System Integration Module (Sim)
SIM memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_8004 Chip Control register (SIM_CHIPCTL) 0000_0000h 5.2.1/68 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 68: Chip Control Register (Sim_Chipctl)
SIM_CHIPCTL contains the controls for selecting ADC COCO trigger, trace clock, clock out source, PDB back-to-back mode and ADC interleave channel. Address: 4004_8000h base + 4h offset = 4004_8004h Reset PDB_ ADC_INTERLEAVE_EN Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 69 Selects the clock to output on the CLKOUT pin. Reserved SCGCLKOUT(SIRC/FIRC/SOSC/LPFLL), see the SCG_CLKOUTCNFG register RTC oscillator (OSC32) clock (32 kHz) LPO clock (128 kHz) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 70: Ftm Option Register 0 (Sim_Ftmopt0)
FTM3 external clock driven by TCLK2 pin. No clock input 29–28 FTM2 External Clock Pin Select FTM2CLKSEL Selects the external pin used to drive the clock to the FTM2 module. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 71 TRGMUX_FTM2 SELx is corresponding to FTM2 Fault x input . Bit value = 0: FTM2_FLTx pin Bit value = 1: TRGMUX_FTM2 out Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 72: Adc Options Register (Sim_Adcopt)
Bit value = 0: FTM0_FLTx pin Bit value = 1: TRGMUX_FTM0 out 5.2.3 ADC Options Register (SIM_ADCOPT) Address: 4004_8000h base + 18h offset = 4004_8018h ADC2SWPRETRG Reset ADC1SWPRETRG ADC0SWPRETRG Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 73 0 software pre-trigger 1 software pre-trigger 2 software pre-trigger 3 ADC1 trigger source select ADC1TRGSEL Selects trigger source for ADC1. PDB output TRGMUX output Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 74: Ftm Option Register 1 (Sim_Ftmopt1)
ADC0 trigger source select ADC0TRGSEL Selects trigger source for ADC0. PDB output TRGMUX output 5.2.4 FTM Option Register 1 (SIM_FTMOPT1) Address: 4004_8000h base + 1Ch offset = 4004_801Ch FTM3_OUTSEL FTM0_OUTSEL Reset Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 75 Software control for FTM2 hardware trigger synchronization No effect. Write 1 to assert the TRIG1 input to FTM2. Software must clear this bit to allow other trigger sources to assert. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 76: System Device Identification Register (Sim_Sdid)
Specifies the Kinetis E-series sub-family of the device. 23–20 Kinetis Series ID SERIESID Specifies the Kinetis series of the device. 0010 Kinetis E+ series Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 77: Platform Clock Gating Control Register (Sim_Platcgc)
Reset Reset SIM_PLATCGC field descriptions Field Description 31–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 78: Flash Configuration Register 1 (Sim_Fcfg1)
5.2.7 Flash Configuration Register 1 (SIM_FCFG1) NOTE Reset value of NVMSIZE, PFSIZE, EEERAM_SIZE, DEPART loaded during System Reset from Flash IFR. Address: 4004_8000h base + 4Ch offset = 4004_804Ch NVMSIZE PFSIZE EEERAMSIZE Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 79 EEE SRAM SIZE EEERAMSIZE EEE SRAM data size . 0000 Reserved 0001 Reserved 0010 4 KB 0011 2 KB 0100 1 KB 0101 512 Bytes Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 80 Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash. Flash is enabled Flash is disabled Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 81: Flash Configuration Register 2 (Sim_Fcfg2)
This field concatenated with 13 trailing zeros indicates the first invalid address of data flash (block 1). Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 82: Unique Identification Register High (Sim_Uidh)
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: • Reset value loaded during System Reset from Flash IFR. SIM_UIDMH field descriptions Field Description UID95_64 Unique Identification Unique identification for the device. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 83: Unique Identification Register Mid Low (Sim_Uidml)
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: • Reset value loaded during System Reset from Flash IFR. SIM_UIDL field descriptions Field Description UID31_0 Unique Identification Unique identification for the device. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 84: System Clock Divider Register 4 (Sim_Clkdiv4)
This field sets the divide value for the fractional clock divider used as a source for trace clock. The source clock for the trace clock is set by the SIM_CHIPCTL[TRACECLK_SEL]. Divider output clock = Divider input clock × [(TRACEFRAC+1)/(TRACEDIV+1)]. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 85: Miscellaneous Control Register (Sim_Misctrl)
Software can send an interrupt to CPU. 15–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Software Trigger bit to TRGMUX SW_TRG Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 86 Memory map and register definition Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 87: Miscellaneous Control Module (Mcm)
E008_000C Core Platform Control Register (MCM_CPCR) 0000_0000h 6.2.3/89 E008_0010 Interrupt Status and Control Register (MCM_ISCR) 0000_0000h 6.2.4/91 E008_0020 Store Buffer Fault address register (MCM_FADR) Undefined 6.2.5/94 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 88: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. A bus slave connection to AXBS input port n is absent A bus slave connection to AXBS input port n is present Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 89: Crossbar Switch (Axbs) Master Configuration (Mcm_Plamc)
Control Register defines the arbitration and protection schemes for the two system RAM arrays. NOTE Bits 23-0 are undefined after reset. Address: E008_0000h base + Ch offset = E008_000Ch SRAMLAP SRAMUAP Reserved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 90 23–10 This field is reserved. Reserved Crossbar round-robin arbitration enable CBRR Configures the crossbar slave ports to fixed-priority or round-robin arbitration. Fixed-priority arbitration Round-robin arbitration Reserved This field is reserved. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 91: Interrupt Status And Control Register (Mcm_Iscr)
FPSCR bit. Address: E008_0000h base + 10h offset = E008_0010h Reset Reset MCM_ISCR field descriptions Field Description FPU input denormal interrupt enable FIDCE Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 92 This read-only bit is a copy of the core’s FPSCR[IXC] bit and signals an inexact number has been detected in the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[IXC] bit. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 93 FADR, FATR, and FDR registers during the interrupt service routine before clearing the CWBER flag. No error Error occurred Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 94: Store Buffer Fault Address Register (Mcm_Fadr)
When a properly-enabled cache write buffer error interrupt event is detected, the faulting attributes are captured in the MCM_FATR register. The bits in this register are set by hardware and signaled by the assertion of MCM_ISCR[CWBER]. Attempted writes have no effect. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 95 Bus error master number BEMN Crossbar switch bus master number of the captured cache write buffer bus error. For this device, this value is always 0x1. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 96: Store Buffer Fault Data Register (Mcm_Fdr)
The bits in this register are set by hardware and signaled by the assertion of MCM_ISCR[CWBER]. For byte and halfword writes, only the accessed byte lanes contain valid data; the contents of the other bytes are undefined. Attempted writes have no effect. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 97: Process Id Register (Mcm_Pid)
This field is reserved. Reserved This read-only field is reserved and always has the value 0. M0_PID And M1_PID For MPU Drives the M0_PID and M1_PID values in the MPU. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 98: Compute Operation Control Register (Mcm_Cpo)
Compute operation entry has completed or compute operation exit has not completed. Compute Operation request CPOREQ This bit is auto-cleared by vector fetching if CPOWOI = 1. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 99: Local Memory Descriptor Register (Mcm_Lmdrn)
Privileged writes from other bus masters are ignored. Attempted user mode accesses or any access with a size other than 32 bits are terminated with an error. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 100 Memory map/register descriptions Address: E008_0000h base + 400h offset + (4d × i), where i=0d to 2d LMSZ Reset Reserved Reset * Notes: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 101 LMEM Data Path Width. This read-only field defines the width of the local memory. 000-001 Reserved LMEMn 32-bits wide LMEMn 64-bits wide 100-111 Reserved Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 102 • CF0[3] - PFE = Parity Fault Enable • CF0[2] - RESERVED • CF0[1] - EERC = ECC Enable Read Check • CF0[0] - EEWG = ECC Enable Write Generation Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 103: Lmem Parity & Ecc Control Register (Mcm_Lmpecr)
7–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Enable RAM ECC Noncorrectable Reporting ERNCR reporting enabled reporting disabled Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 104: Lmem Parity & Ecc Interrupt Register (Mcm_Lmpeir)
• PEIR[15:10] - Reserved • PEIR[9] - 1-bit Error detected on SRAM_U • PEIR[8] - 1-bit Error detected on SRAM_L ENCn = ECC Noncorrectable Error n Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 105: Lmem Fault Address Register (Mcm_Lmfar)
• PEIR[0] - Noncorrectable Error detected on SRAM_L 6.2.13 LMEM Fault Address Register (MCM_LMFAR) Address: E008_0000h base + 490h offset = E008_0490h EFADD Reset MCM_LMFAR field descriptions Field Description EFADD ECC Fault Address Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 106: Lmem Fault Attribute Register (Mcm_Lmfatr)
This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–8 Parity/ECC Fault Master Number PEFMST Parity/ECC Fault Write PEFW Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 107: Lmem Fault Data High Register (Mcm_Lmfdhr)
Parity or ECC Fault Data High 6.2.16 LMEM Fault Data Low Register (MCM_LMFDLR) Address: E008_0000h base + 4A4h offset = E008_04A4h PEFDL Reset MCM_LMFDLR field descriptions Field Description PEFDL Parity or ECC Fault Data Low Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 108: Functional Description
1. From MCM_ISCR[31:16] && MCM_ISCR[15:0] 2. Search the result for asserted flags, which indicate the exact interrupt sources NOTE ECC and Parity interrupts are determined by LMEPECR (interrupt enable) and LMPEIR (interrupt source). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 109: Crossbar Switch Lite (Axbs-Lite)
Slave port number Protected by MPU? Flash memory controller SRAM controllers Peripheral bridge 0 / GPIO No. Protection built into Peripheral Bridge (AIPS). 1. See System memory map for access restrictions. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 110: Introduction
This crossbar switch is designed for minimal gate count. It, therefore, has no memory- mapped configuration registers. Please see the chip-specific information for information on whether the arbitration method in the crossbar switch is programmable, and by which module. 7.4 Functional Description Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 111: General Operation
7.4.2 Arbitration The crossbar switch supports two arbitration algorithms: • Fixed priority • Round-robin The selection of the global slave port arbitration algorithm is described in the crossbar switch chip-specific information. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 112 The requesting master's priority level is lower than the current At the conclusion of one of the following cycles: master. • An IDLE cycle • A non-IDLE cycle to a location other than the current slave port Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 113: Initialization/Application Information
7.5 Initialization/application information No initialization is required for the crossbar switch. See the chip-specific crossbar switch information for the reset state of the arbitration scheme. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 114 Initialization/application information Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 115: Memory Protection Unit (Mpu)
8.1.1.2 MPU Logical Bus Master Assignments The logical bus master assignments for the MPU are: Table 8-2. MPU Logical Bus Master Assignments MPU Logical Bus Master Number Bus Master Core Debugger Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 116: Introduction
Address Phase Signals Peripheral Bus Access Region Evaluation Descriptor 0 Macro Access Region Evaluation Descriptor 1 Macro Access Region Evaluation Descriptor x Macro MPU_EARn MPU_EDRn Figure 8-1. MPU block diagram Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 117: Features
If an access error occurs, the reference is terminated with an error response, and the MPU inhibits the bus cycle being sent to the targeted slave device. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 118: Memory Map/Register Definition
4000_D028 Error Address Register, slave port n (MPU_EAR3) 0000_0000h 8.4.2/121 4000_D02C Error Detail Register, slave port n (MPU_EDR3) 0000_0000h 8.4.3/122 4000_D400 Region Descriptor n, Word 0 (MPU_RGD0_WORD0) 0000_0000h 8.4.4/123 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 119 8.4.8/128 (MPU_RGDAAC1) Region Descriptor Alternate Access Control n 4000_D808 See section 8.4.8/128 (MPU_RGDAAC2) Region Descriptor Alternate Access Control n 4000_D80C See section 8.4.8/128 (MPU_RGDAAC3) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 120: Control/Error Status Register (Mpu_Cesr)
This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 1. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 121: Error Address Register, Slave Port N (Mpu_Earn)
Address: 4000_D000h base + 10h offset + (8d × i), where i=0d to 3d EADDR Reset MPU_EARn field descriptions Field Description EADDR Error Address Indicates the reference address from slave port n that generated the access error Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 122: Error Detail Register, Slave Port N (Mpu_Edrn)
Indicates attribute information about the faulting reference. NOTE: All other encodings are reserved. User mode, instruction access User mode, data access Supervisor mode, instruction access Supervisor mode, data access Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 123: Region Descriptor N, Word 0 (Mpu_Rgdn_Word0)
Defines the most significant bits of the 0-modulo-32 byte start address of the memory region. Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 124: Region Descriptor N, Word 1 (Mpu_Rgdn_Word1)
For the privilege rights of bus masters 0–3, there are three flags associated with this function: • Read (r) refers to accessing the referenced memory address using an operand (data) fetch Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 125 Bus Master 6 Write Enable M6WE Bus master 6 writes terminate with an access error and the write is not performed Bus master 6 writes allowed Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 126 See M3SM description. 14–12 Bus Master 2 User Mode Access control M2UM See M3UM description. Bus Master 1 Process Identifier enable M1PE See M3PE description. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 127: Region Descriptor N, Word 3 (Mpu_Rgdn_Word3)
Specifies the process identifier that is included in the region hit determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this field. 23–16 Process Identifier Mask PIDMASK Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 128: Region Descriptor Alternate Access Control N (Mpu_Rgdaacn)
Address: 4000_D000h base + 800h offset + (4d × i), where i=0d to 7d M3SM M3UM Reset M2UM M1SM M1UM M0SM M0UM Reset * Notes: • Reset value of RGDAAC0 is 0061_F7DFh Reset value of RGDAAC[1:7] is 0000_0000h Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 129 (r), write (w), and execute (x) permissions. In M3UM[2:0]: M3UM[2] controls read permissions, M3UM[1] controls write permissions, and M3UM[0] controls execute permissions. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 130: Functional Description
As shown in the following figure, the access evaluation macro inputs the crossbar bus address phase signals and the contents of a region descriptor (RGDn) and performs two major functions: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 131 PID and PIDMASK fields. A process identifier hit term is formed as follows: pid_hit = ~RGDn_Word2[MxPE] | ((current_pid | RGDn_Word3[PIDMASK]) == (RGDn_Word3[PID] | RGDn_Word3[PIDMASK])) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 132: Putting It All Together And Error Terminations
• If the access hits in a single region descriptor and that region signals a protection violation, a protection error is reported. • If the access hits in multiple (overlapping) regions and all regions signal protection violations, a protection error is reported. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 133: Power Management
(RGDAACn), so there are no coherency issues involved with the update. When the write completes, the memory region's access rights switch instantaneously to the new value. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 134 — — CP0 → CP1 shared data — — CP1 → CP0 shared data CP1 data & stack — — — Shared DMA data — — Peripheral space Peripherals — Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 135: Usage Guide
Access violations detected by the MPU are signaled to the appropriate bus master as shown below: Table 8-5. Access Violation Indications Bus Master Core Indication Core Bus fault (interrupt vector #5) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 136: Reset Values For Rgd0 Registers
These protections (summarized below) guarantee that the debugger always has access to the entire address space and those rights cannot be changed by the core or any other bus master. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 137 Partial. The Core cannot write to the following registers or register fields: • RGD0_WORD0, RGD0_WORD1, RGD0_WORD3 • RGD0_WORD2[M1SM, M1UM] • RGDAAC0[M1SM, M1UM] NOTE: Changes to the RGD0_WORD2 alterable fields should be done via a write to RGDAAC0. Debugger Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 138 Usage Guide Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 139: Peripheral Bridge (Aips-Lite)
4 KB. (It might be possible that all the peripheral slots are not used. See the memory map chapter for details on slot assignments.) The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 140: Features
See section 9.3.3/149 (AIPS_OPACRA) Off-Platform Peripheral Access Control Register 4000_0044 See section 9.3.3/149 (AIPS_OPACRB) Off-Platform Peripheral Access Control Register 4000_0048 See section 9.3.3/149 (AIPS_OPACRC) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 141: Master Privilege Register A (Aips_Mpra)
A register field that maps to an unimplemented master or peripheral behaves as read- only-zero. Each master is assigned a logical ID from 0 to 15. See the master logical ID assignment table in the chip-specific AIPS information. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 142 This master is not trusted for read accesses. This master is trusted for read accesses. Master 1 Trusted for Writes MTW1 Determines whether the master is trusted for write accesses. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 143 This read-only field is reserved and always has the value 0. 6–4 This field is reserved. Reserved This field is reserved. Reserved This read-only field is reserved and always has the value 0. Reserved This field is reserved. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 144: Peripheral Access Control Register (Aips_Pacrn)
MPRx[MPLn] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 145 MPRx[MPLn] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 146 MPRx[MPLn] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 147 MPRx[MPLn] control field for the master must be set. If not, access terminates with an error response and no peripheral access initiates. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 148 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 149: Off-Platform Peripheral Access Control Register (Aips_Opacrn)
Address: 4000_0000h base + 40h offset + (4d × i), where i=0d to 11d Reset Reset * Notes: • The reset value is chip-dependent and can be found in the AIPS chip-specific information. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 150 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 151 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 152 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 153 Accesses from an untrusted master are allowed. Accesses from an untrusted master are not allowed. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 154: Peripheral Access Control Register (Aips_Pacru)
Accesses from an untrusted master are not allowed. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 155: Functional Description
Misaligned accesses are supported to allow memory to be placed on the slave peripheral bus. Peripheral registers must not be misaligned, although no explicit checking is performed by the peripheral bridge. All accesses are performed with a single transfer. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 156 All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted that is larger than the targeted port, an error response is generated. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 157: Trigger Mux Control (Trgmux)
1-1 paired up, and are both selected by the same trigger control register. Not every module has pre-trigger input, please refer to the respective module chapter for details. Following is the main structure of TRGMUX, and take ModuleA as an example. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 158 VSS trigger VDD trigger SIM_SW_TRG Software trigger controlled by SIM module TRGMUX_INx TRGMUX external trigger input x LPUARTx_RX_data LPUARTx receive end of word trigger Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 159 LPTMRx timer counter match trigger LPIT_CHx LPIT channel x timer counter match trigger FTMx_TRIG FTMx timer counter match trigger CMPx_OUT CMPx output trigger FlexIO_TRIGx FlexIO timer x counter match trigger Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 160 FTM3_FAULT1 ADC2_COCOB ---------> in30 out54 ----------------------> FTM3_FAULT2 ---------> in31 out55 TRGMUX_PDB0 out56 ----------------------> PDB0_TRG_IN out57 X out58 X out59 X ----------------------> PDB1_TRG_IN TRGMUX_PDB1 out60 out61 X out62 X out63 X Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 161 ADC, while the pre-triggers are not OR'ed. The LPIT pre-triggers can be pre-triggers for each ADC. There is another PDB pre-trigger scheme existing on this device, which is not through Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 162: Introduction
See each peripheral's TRGMUX register for details. 10.4 Memory map and register definition The TRGMUX module contains register fields for selecting the trigger input for peripheral modules. 10.4.1 TRGMUX0 Register Descriptions Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 163 001_1100 - (0x1C) Unused. 001_1101 - (0x1D) Unused. 001_1110 - (0x1E) Unused. 001_1111 - (0x1F) Unused. 010_0000 - (0x20) Unused 010_0001 - (0x21) Unused 010_0010 - (0x22) Unused 010_0011 - (0x23) Unused Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 164 100_0010 - (0x42) Unused 100_0011 - (0x43) Unused 100_0100 - (0x44) Unused 100_0101 - (0x45) Unused 100_0110 - (0x46) Unused 100_0111 - (0x47) Unused 100_1000 - (0x48) Unused 100_1001 - (0x49) Unused Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 165 110_1000 - (0x68) Unused 110_1001 - (0x69) Unused 110_1010 - (0x6A) Unused 110_1011 - (0x6B) Unused 110_1100 - (0x6C) Unused 110_1101 - (0x6D) Unused 110_1110 - (0x6E) Unused 110_1111 - (0x6F) Unused Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 166 TRGMUX PDB0 (TRGMUX_PDB0) 00000000h 4006203Ch TRGMUX PDB1 (TRGMUX_PDB1) 00000000h 40062040h TRGMUX PDB2 (TRGMUX_PDB2) 00000000h 40062044h TRGMUX FLEXIO (TRGMUX_FLEXIO) 00000000h 40062048h TRGMUX LPIT0 (TRGMUX_LPIT0) 00000000h Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 167 10.4.1.2 TRGMUX DMAMUX0 (TRGMUX_DMAMUX0) 10.4.1.2.1 Address Register Offset TRGMUX_DMAMUX0 40062000h 10.4.1.2.2 Function TRGMUX Register 10.4.1.2.3 Diagram Bits Rese SEL3 SEL2 rved Reset Bits Rese Rese SEL1 SEL0 rved rved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 168 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.3 TRGMUX EXTOUT0 (TRGMUX_EXTOUT0) 10.4.1.3.1 Address Register Offset TRGMUX_EXTOUT0 40062004h TRGMUX Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 169 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.4 TRGMUX EXTOUT1 (TRGMUX_EXTOUT1) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 170 Select Bit Fields table in the Features section for bit field information. This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 171 Select Bit Fields table in the Features section for bit field information. This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 172 Select Bit Fields table in the Features section for bit field information. 10.4.1.6 TRGMUX ADC1 (TRGMUX_ADC1) 10.4.1.6.1 Address Register Offset TRGMUX_ADC1 40062010h TRGMUX Register 10.4.1.6.2 Diagram Bits Rese SEL3 SEL2 rved Reset Bits Rese Rese SEL1 SEL0 rved rved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 173 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.7 TRGMUX ADC2 (TRGMUX_ADC2) 10.4.1.7.1 Address Register Offset TRGMUX_ADC2 40062014h TRGMUX Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 174 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.8 TRGMUX DAC0 (TRGMUX_DAC0) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 175 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 176 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 177 1b - Register cannot be written until the next system Reset. 30-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 178 Select Bit Fields table in the Features section for bit field information. 10.4.1.11 TRGMUX CMP2 (TRGMUX_CMP2) 10.4.1.11.1 Address Register Offset TRGMUX_CMP2 40062024h TRGMUX Register 10.4.1.11.2 Diagram Bits Rese Reserved Reserved rved Reset Bits Rese Rese Reserved SEL0 rved rved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 179 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.12 TRGMUX FTM0 (TRGMUX_FTM0) 10.4.1.12.1 Address Register Offset TRGMUX_FTM0 40062028h TRGMUX Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 180 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.13 TRGMUX FTM1 (TRGMUX_FTM1) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 181 Select Bit Fields table in the Features section for bit field information. This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 182 Select Bit Fields table in the Features section for bit field information. This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 183 Select Bit Fields table in the Features section for bit field information. 10.4.1.15 TRGMUX FTM3 (TRGMUX_FTM3) 10.4.1.15.1 Address Register Offset TRGMUX_FTM3 40062034h TRGMUX Register 10.4.1.15.2 Diagram Bits Rese SEL3 SEL2 rved Reset Bits Rese Rese SEL1 SEL0 rved rved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 184 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.16 TRGMUX PDB0 (TRGMUX_PDB0) 10.4.1.16.1 Address Register Offset TRGMUX_PDB0 40062038h TRGMUX Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 185 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.17 TRGMUX PDB1 (TRGMUX_PDB1) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 186 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 187 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 188 0b - Register can be written. 1b - Register cannot be written until the next system Reset. 30-24 Trigger MUX Input 3 Source Select Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 189 Select Bit Fields table in the Features section for bit field information. 10.4.1.20 TRGMUX LPIT0 (TRGMUX_LPIT0) 10.4.1.20.1 Address Register Offset TRGMUX_LPIT0 40062048h TRGMUX Register 10.4.1.20.2 Diagram Bits Rese SEL3 SEL2 rved Reset Bits Rese Rese SEL1 SEL0 rved rved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 190 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.21 TRGMUX LPUART0 (TRGMUX_LPUART0) 10.4.1.21.1 Address Register Offset TRGMUX_LPUART0 4006204Ch TRGMUX Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 191 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.22 TRGMUX LPUART1 (TRGMUX_LPUART1) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 192 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 193 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 194 1b - Register cannot be written until the next system Reset. 30-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 195 Select Bit Fields table in the Features section for bit field information. 10.4.1.25 TRGMUX LPSPI0 (TRGMUX_LPSPI0) 10.4.1.25.1 Address Register Offset TRGMUX_LPSPI0 4006205Ch TRGMUX Register 10.4.1.25.2 Diagram Bits Rese Reserved Reserved rved Reset Bits Rese Rese Reserved SEL0 rved rved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 196 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.26 TRGMUX LPSPI1 (TRGMUX_LPSPI1) 10.4.1.26.1 Address Register Offset TRGMUX_LPSPI1 40062060h TRGMUX Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 197 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 10.4.1.27 TRGMUX LPTMR0 (TRGMUX_LPTMR0) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 198 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 199 This read-only bit field is reserved and always has the value 0. — 14-8 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 200 1b - Register cannot be written until the next system Reset. 30-24 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 201: Trgmux1 Register Descriptions
000_1011 - (0x0B) LPI2C0 Slave STOP is selected. 000_1100 - (0x0C) LPSPI0 Frame is selected. 000_1101 - (0x0D) LPSPI0 RX data is selected. 000_1110 - (0x0E) LPUART1 RX Data is selected. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 202 010_1101 - (0x2D) Unused 010_1110 - (0x2E) Unused 010_1111 - (0x2F) Unused 011_0000 - (0x30) Unused 011_0001 - (0x31) Unused 011_0010 - (0x32) Unused 011_0011 - (0x33) Unused 011_0100 - (0x34) Unused Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 203 101_0011 - (0x53) Unused 101_0100 - (0x54) Unused 101_0101 - (0x55) Unused 101_0110 - (0x56) Unused 101_0111 - (0x57) Unused 101_1000 - (0x58) Unused 101_1001 - (0x59) Unused 101_1010 - (0x5A) Unused Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 204 111_1000 - (0x78) Unused 111_1001 - (0x79) Unused 111_1010 - (0x7A) Unused 111_1011 - (0x7B) Unused 111_1100 - (0x7C) Unused 111_1101 - (0x7D) Unused 111_1110 - (0x7E) Unused 111_1111 - (0x7F) Unused Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 205 0b - Register can be written. 1b - Register cannot be written until the next system Reset. 30-24 Trigger MUX Input 3 Source Select SEL3 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 206 Select Bit Fields table in the Features section for bit field information. 10.4.2.3 TRGMUX CTRL1 (TRGMUX_CTRL1) 10.4.2.3.1 Address Register Offset TRGMUX_CTRL1 40063004h TRGMUX Register 10.4.2.3.2 Diagram Bits Rese SEL3 SEL2 rved Reset Bits Rese Rese SEL1 SEL0 rved rved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 207: Usage Guide
TRGMUX. 10.5.1 ADC Trigger Source The following triggers are via the TRGMUX: • CMP out to trigger each ADC • LPIT capable to trigger each ADC Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 208: Cmp Window/Sample Input
For details, please refer to “Window Mode” section in the CMP chapter. 10.5.3 FTM Fault Detection Input / Hardware Triggers and Synchronization Please refer to the FTM chapter for more details. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 209: Direct Memory Access Multiplexer (Dmamux)
Source description Async DMA number capable — Channel disabled Reserved — LPUART0 Receive LPUART0 Transmit LPUART1 Receive LPUART1 Transmit LPUART2 Receive LPUART2 Transmit Reserved — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 210 FTM3 Channel 5 FTM3 Channel 6 FTM3 Channel 7 ADC0 ADC0 COCO ADC1 ADC1 COCO ADC2 ADC2 COCO CMP0 — CMP1 — CMP2 — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 211 LPIT can trigger DMA via TRGMUX. Table 11-2. DMAMUX trigger sources Trigger number Trigger module Trigger description TRGMUX TRGMUX trigger out0 TRGMUX TRGMUX trigger out1 TRGMUX TRGMUX trigger out2 TRGMUX TRGMUX trigger out3 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 212: Introduction
The DMAMUX module provides these features: • Up to 63 peripheral slots and up to two always-on slots can be routed to 16 channels. • 16 independently selectable DMA channel routers. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 213 (LPIT). This mode is available only for channels 0–3. 11.3 External signal description The DMAMUX has no external pins. 11.4 Memory map/register definition This section provides a detailed description of all memory-mapped registers in the DMAMUX. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 214 Before changing the trigger or source settings, a DMA channel must be disabled via CHCFGn[ENBL]. Address: 4002_1000h base + 0h offset + (1d × i), where i=0d to 15d Read ENBL TRIG SOURCE Write Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 215 Besides the normal routing functionality, the first 4 channels of the DMAMUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames, or packets at fixed intervals without the need for processor intervention. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 216 This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in the following figure. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 217 DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in on- chip memory. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 218 DMA transfer will impose on the system. For this option, the DMA channel must be disabled in the DMA channel MUX. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 219 4. Configure the corresponding timer. 5. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 220 The following code example illustrates steps 1 and 3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0x40021000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCFG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 221 *CHCFG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCFG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCFG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 222 *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 223 • Local memory containing transfer control descriptors for each of the 16 channels 12.1.1 eDMA system block diagram Figure 12-1 illustrates the components of the eDMA system, including the eDMA module ("engine"). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 224 After the minor loop completes execution, the address path hardware writes Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 225 The eDMA module features: • All data movement via dual-address transfers: read from source, write to destination • Programmable source and destination addresses and transfer size • Support for enhanced addressing modes Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 226 • Support for complex data structures In the discussion of this module, n is used to reference the channel number. 12.2 Modes of operation The eDMA operates in the following modes: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 227 0, channel 1, ... channel 15. Each TCDn definition is presented as 11 registers of 16 or 32 bits. 12.3.2 TCD initialization Prior to activating a channel, you must initialize its TCD with the appropriate transfer profile. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 228 0000_0000h 12.3.8/246 4000_8018 Clear Enable Error Interrupt Register (DMA_CEEI) (always 12.3.9/249 reads 0) 4000_8019 Set Enable Error Interrupt Register (DMA_SEEI) (always 12.3.10/250 reads 0) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 229 12.3.21/266 4000_9000 TCD Source Address (DMA_TCD0_SADDR) Undefined 12.3.22/267 4000_9004 TCD Signed Source Address Offset (DMA_TCD0_SOFF) Undefined 12.3.23/267 4000_9006 TCD Transfer Attributes (DMA_TCD0_ATTR) Undefined 12.3.24/268 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 230 TCD Current Minor Loop Link, Major Loop Count (Channel 4000_9036 Undefined 12.3.31/274 Linking Enabled) (DMA_TCD1_CITER_ELINKYES) 4000_9036 DMA_TCD1_CITER_ELINKNO Undefined 12.3.32/275 TCD Last Destination Address Adjustment/Scatter Gather 4000_9038 Undefined 12.3.33/276 Address (DMA_TCD1_DLASTSGA) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 231 TCD Signed Minor Loop Offset (Minor Loop Mapping 4000_9068 Enabled and Offset Disabled) Undefined 12.3.26/270 (DMA_TCD3_NBYTES_MLOFFNO) TCD Signed Minor Loop Offset (Minor Loop Mapping and 4000_9068 Undefined 12.3.27/271 Offset Enabled) (DMA_TCD3_NBYTES_MLOFFYES) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 232 12.3.35/279 (DMA_TCD4_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 4000_909E Undefined 12.3.36/280 (Channel Linking Disabled) (DMA_TCD4_BITER_ELINKNO) 4000_90A0 TCD Source Address (DMA_TCD5_SADDR) Undefined 12.3.22/267 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 233 TCD Signed Destination Address Offset 4000_90D4 Undefined 12.3.30/273 (DMA_TCD6_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_90D6 Undefined 12.3.31/274 Linking Enabled) (DMA_TCD6_CITER_ELINKYES) 4000_90D6 DMA_TCD6_CITER_ELINKNO Undefined 12.3.32/275 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 234 TCD Minor Byte Count (Minor Loop Mapping Disabled) 4000_9108 Undefined 12.3.25/269 (DMA_TCD8_NBYTES_MLNO) TCD Signed Minor Loop Offset (Minor Loop Mapping 4000_9108 Enabled and Offset Disabled) Undefined 12.3.26/270 (DMA_TCD8_NBYTES_MLOFFNO) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 235 Address (DMA_TCD9_DLASTSGA) 4000_913C TCD Control and Status (DMA_TCD9_CSR) Undefined 12.3.34/277 TCD Beginning Minor Loop Link, Major Loop Count 4000_913E (Channel Linking Enabled) Undefined 12.3.35/279 (DMA_TCD9_BITER_ELINKYES) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 236 TCD Signed Minor Loop Offset (Minor Loop Mapping and 4000_9168 Undefined 12.3.27/271 Offset Enabled) (DMA_TCD11_NBYTES_MLOFFYES) TCD Last Source Address Adjustment 4000_916C Undefined 12.3.28/272 (DMA_TCD11_SLAST) 4000_9170 TCD Destination Address (DMA_TCD11_DADDR) Undefined 12.3.29/273 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 237 TCD Beginning Minor Loop Link, Major Loop Count 4000_919E (Channel Linking Disabled) Undefined 12.3.36/280 (DMA_TCD12_BITER_ELINKNO) 4000_91A0 TCD Source Address (DMA_TCD13_SADDR) Undefined 12.3.22/267 4000_91A4 TCD Signed Source Address Offset (DMA_TCD13_SOFF) Undefined 12.3.23/267 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 238 TCD Signed Destination Address Offset 4000_91D4 Undefined 12.3.30/273 (DMA_TCD14_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_91D6 Undefined 12.3.31/274 Linking Enabled) (DMA_TCD14_CITER_ELINKYES) 4000_91D6 DMA_TCD14_CITER_ELINKNO Undefined 12.3.32/275 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 239 (DMA_TCD15_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 4000_91FE (Channel Linking Disabled) Undefined 12.3.36/280 (DMA_TCD15_BITER_ELINKNO) 12.3.5 Control Register (DMA_CR) The CR defines the basic operating configuration of the DMA. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 240 When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. Address: 4000_8000h base + 0h offset = 4000_8000h Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 241 HALT Normal operation Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 242 • A cancel transfer with error bit that will be set when a transfer is canceled via the corresponding cancel transfer control bit Fault reporting and handling for more details. Address: 4000_8000h base + 4h offset = 4000_8004h Reset ERRCHN Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 243 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. • TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 244 NOTE Disable a channel’s hardware service request at the source before clearing the channel’s ERQ bit. Address: 4000_8000h base + Ch offset = 4000_800Ch Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 245 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 6 ERQ6 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 246 EEI register. The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 247 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 8 EEI8 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 248 Enable Error Interrupt 0 EEI0 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 249 Clear only the EEI bit specified in the CEEI field Clear all bits in EEI 5–4 This field is reserved. Reserved CEEI Clear Enable Error Interrupt Clears the corresponding bit in EEI Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 250 ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 251 This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: 4000_8000h base + 1Bh offset = 4000_801Bh Read Write SAER SERQ Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 252 Clears All DONE Bits CADN Clears only the TCDn_CSR[DONE] bit specified in the CDNE field Clears all bits in TCDn_CSR[DONE] 5–4 This field is reserved. Reserved Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 253 Set only the TCDn_CSR[START] bit specified in the SSRT field Set all bits in TCDn_CSR[START] 5–4 This field is reserved. Reserved SSRT Set START Bit Sets the corresponding bit in TCDn_CSR[START] Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 254 Clear only the ERR bit specified in the CERR field Clear all bits in ERR 5–4 This field is reserved. Reserved CERR Clear Error Indicator Clears the corresponding bit in ERR Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 255 Clear only the INT bit specified in the CINT field Clear all bits in INT 5–4 This field is reserved. Reserved CINT Clear Interrupt Request Clears the corresponding bit in INT Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 256 Reset Reset DMA_INT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 257 The interrupt request for corresponding channel is active Interrupt Request 4 INT4 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 258 A zero in any bit position has no affect on the corresponding channel’s current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 259 An error in this channel has occurred Error In Channel 10 ERR10 An error in this channel has not occurred An error in this channel has occurred Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 260 An error in this channel has not occurred An error in this channel has occurred Error In Channel 0 ERR0 An error in this channel has not occurred An error in this channel has occurred Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 261 Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Hardware Request Status Channel 15 HRS15 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 262 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 263 A hardware service request for channel 3 is not present A hardware service request for channel 3 is present Hardware Request Status Channel 2 HRS2 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 264 Reset Reset DMA_EARS field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 265 Enable asynchronous DMA request in stop mode for channel 4 EDREQ_4 Disable asynchronous DMA request for channel 4. Enable asynchronous DMA request for channel 4. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 266 Channel n cannot be suspended by a higher priority channel’s service request. Channel n can be temporarily suspended by the service request of a higher priority channel. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 267 12.3.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF) Address: 4000_8000h base + 1004h offset + (32d × i), where i=0d to 15d Read SOFF Write Reset * Notes: • x = Undefined at reset. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 268 The eDMA defaults to privileged data access for all transactions. 8-bit 16-bit 32-bit Reserved 16-byte burst 32-byte burst Reserved Reserved 7–3 Destination Address Modulo DMOD See the SMOD definition Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 269 TCD memory. If the major iteration count is completed, additional processing is performed. NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 270 The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable DMLOE Selects whether the minor loop offset is applied to the destination address upon minor loop completion. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 271 TCD_NBYTES_MLOFFNO register description. If minor loop mapping is disabled, then refer to the TCD_NBYTES_MLNO register description. Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d MLOFF Reset MLOFF NBYTES Reset * Notes: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 272 This register uses two's complement notation; the overflow bit is discarded. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 273 = Undefined at reset. DMA_TCDn_DOFF field descriptions Field Description DOFF Destination Address Signed Offset Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 274 CITER field from the Beginning Iteration Count (BITER) field. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 275 It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations, for Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 276 This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, otherwise a configuration error is reported. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 277 This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count reaches zero. The software clears it, or the hardware when the channel is activated. The access of this field is W0C, write-zero-to-clear. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 278 If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero. The end-of-major loop interrupt is disabled. The end-of-major loop interrupt is enabled. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 279 CITER field. The channel-to-channel linking is disabled The channel-to-channel linking is enabled 14–13 This field is reserved. Reserved 12–9 Link Channel Number LINKCH Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 280 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 281 12.4.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 282 The following diagram illustrates the second part of the basic data flow: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 283 (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 284 Each of these possible causes are detailed below: • The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. • The minor loop byte count must be a multiple of the source and destination transfer sizes. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 285 Due to pipeline effect, the next transfer is already in progress when the bus error is received by the eDMA. If a bus error Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 286 If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 287 12.4.4.1 Peak transfer rates The peak transfer rates for several different source and destination transfers are shown in the following tables. These tables assume: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 288 SRAM. The same timing assumptions used in the previous example apply to this calculation. In particular, this metric also reflects the time required to activate the channel. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 289 Assuming zero wait states on the system bus, DMA requests can be processed every 9 cycles. Assuming an average of the access times associated with internal peripheral bus- to-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 290 • All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states viewed from the system bus data phase • System operates at 150 MHz For an SRAM to internal peripheral bus transfer, Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 291 1. Write to the CR if a configuration other than the default is desired. 2. Write the channel priority levels to the DCHPRIn registers if a configuration other than the default is desired. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 292 CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 293 The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 294 (TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 295 Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 296 Write 32-bits to location 0x2004 → second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 297 Write 32-bits to location 0x201C → last iteration of the minor loop → major loop complete. 14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 298 There are two methods to test for minor loop completion when using software initiated service requests. The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 299 NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 300 TCDn_CITER[E_LINK] = 1 TCDn_CITER[LINKCH] = 0xC TCDn_CITER[CITER] value = 0x4 TCDn_CSR[MAJOR_E_LINK] = 1 TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as: 1. Minor loop done → set TCD12_CSR[START] bit Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 301 This section provides recommended methods to change the programming model during channel execution. 12.5.7.1 Dynamically changing the channel priority The following two options are recommended for dynamically changing channel priority levels: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 302 NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link bit. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 303 1. When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for each TCD associated with a channel using dynamic scatter/gather. 2. Write 1b to the TCD.d_req bit. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 304 If e_sg = 0b, read the 32 bit TCD dlast_sga field. If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 305 TXFIFO upon the request. If the user needs to suspend the DMA/SPI transfer loop, perform the following steps: 1. Disable the DMA service request at the source by writing 0 to SPI_RSER[TFFF_RE]. Confirm that SPI_RSER[TFFF_RE] is 0. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 306 Using DMA for pulse counting on Kinetis • Using DMA and GPIO to emulate timer functionality on Kinetis Family devices • Using DMA to Emulate ADC Flexible Scan Mode on Kinetis K Series Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 307 4G bytes (32-bit address) contiguous memory space. This chapter describes the memory and peripheral locations within that memory space. The following figure shows the system memory and peripheral locations. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 308 LPI2C0 0x4006_7000 0xFFFF_FFFF LPI2C1 0x4006_8000 Reserved 0x4006_A000 LPUART0 0x4006_B000 LPUART1 0x4006_C000 LPUART2 0x4006_D000 Reserved 0x4007_3000 CMP0 0x4007_4000 CMP1 0x4007_5000 CMP2 0x4007_6000 Reserved 0x4007_D000 0x4007_E000 0x4007_F000 0x4007_FFFF Figure 13-1. Memory map Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 309 Address range (KB) KE1xF512VLL15 0x0000_0000–0x0007_FFFF (P-Flash) 0x1000_0000–0x1000_FFFF (FlexNVM) 0x1400_0000–0x1400_0FFF (FlexRAM) KE1xF512VLH15 0x0000_0000–0x0007_FFFF (P-Flash) 0x1000_0000–0x1000_FFFF (FlexNVM) 0x1400_0000–0x1400_0FFF (FlexRAM) KE1xF256VLL15 0x0000_0000–0x0003_FFFF (P-Flash) 0x1000_0000–0x1000_FFFF (FlexNVM) 0x1400_0000–0x1400_0FFF (FlexRAM) KE1xF256VLH15 0x0000_0000–0x0003_FFFF (P-Flash) 0x1000_0000–0x1000_FFFF (FlexNVM) 0x1400_0000–0x1400_0FFF (FlexRAM) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 310 (KB) (KB) MKE1xF512VLL15 0x1FFF_8000-0x2000_7FFF MKE1xF512VLH15 0x1FFF_8000-0x2000_7FFF MKE1xF256VLL15 0x1FFF_C000-0x2000_3FFF MKE1xF256VLH15 0x1FFF_C000-0x2000_3FFF 13.3.2 SRAM retention in low power modes The SRAM is retained power on to all power modes on this device. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 311 SRAM arrays. The two arrays should be treated as separate memory ranges for burst accesses. 13.3.4 SRAM arbitration and priority control The MCM_CPCR register controls the arbitration and priority schemes for the two SRAM arrays. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 312 Cortex-M4 core only 0x2400_0000-0x2FFF_FFFF Reserved – 0x3000_0000-0x33FF_FFFF Reserved – 0x3400_0000-0x3FFF_FFFF Reserved – 0x4000_0000–0x4007_FFFF Bitband region for peripheral bridge (AIPS-Lite) Cortex-M4 core & 0x4008_0000–0x400F_EFFF Reserved – Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 313 • Writing a value with bit 0 set writes a 1 to the target bit. • Writing a value with bit 0 clear writes a 0 to the target bit. A 32-bit read in the alias region returns either: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 314 For programming model accesses via the peripheral bridges, there is generally only a small range within the 4 KB slots that is implemented. Accessing an address that is not implemented in the peripheral results in a transfer error termination. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 315 0x4001_9000 — 0x4001_A000 — 0x4001_B000 — 0x4001_C000 — 0x4001_D000 — 0x4001_E000 — 0x4001_F000 — 0x4002_0000 Flash memory 0x4002_1000 DMA channel mutiplexer 0 0x4002_2000 — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 316 0x4004_1000 — 0x4004_2000 — 0x4004_3000 — 0x4004_4000 — 0x4004_5000 — 0x4004_6000 — 0x4004_7000 — 0x4004_8000 System integration module (SIM) 0x4004_9000 Port A multiplexing control Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 317 Low Power UART (LPUART 0) 0x4006_B000 Low Power UART (LPUART 1) 0x4006_C000 Low Power UART (LPUART 2) 0x4006_D000 — 0x4006_E000 — 0x4006_F000 — 0x4007_0000 — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 318 System Control Space (SCS) (for NVIC and FPU) 0xE000_F000–0xE003_FFFF Reserved 0xE004_0000–0xE004_0FFF Trace Port Interface Unit (TPIU) 0xE004_1000–0xE004_1FFF Reserved 0xE004_2000–0xE004_2FFF Reserved 0xE004_3000–0xE004_3FFF Reserved 0xE004_4000–0xE007_FFFF Reserved Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 319 1. The ARM Core ROM table is optionally required by ARM CoreSight debug infrastructure to discover the components on the chip. This ROM table has no any relationship with the MCU Boot ROM. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 320 Private Peripheral Bus (PPB) memory map Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 321 Reserved region – 0x8000_0000–0x8FFF_FFFF Reserved region – 0x9000_0000–0x9FFF_FFFF Reserved region – 1. Cache write hits do not write-through to program flash or FlexNVM regions because flash writes require flash programming. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 322 • Two output ports are the CCM (Core Code Master) bus used for PC accesses that do not hit the PC cache or SRAM_L or are non-cacheable and the CSM (Core System Master) bus used for PS references that do not hit the SRAM_U. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 323 • Temporal locality — An access to an area of memory is likely to be repeated within a short time period (for example, execution of a code loop). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 324 2. Non-cacheable — access to address spaces with this cache mode are not cacheable. These accesses bypass the cache and access the output bus. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 325 NOTE: This bit stays set until the command completes. Writing zero has no effect. Write: no effect. Read: no cache command active. Write: initiate command indicated by bits 27-24. Read: cache command active. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 326 If a physical address is specified, both ways of the cache are searched, and the command is only performed on the way which hits. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 327 When using the physical address, both ways are searched and the command is performed only if a hit. Cache address Physical address 25–24 Line Command LCMD Search and read or write Invalidate Push Clear Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 328 NOTE: This bit stays set until the command completes. Writing zero has no effect. NOTE: This bit is shared with CSAR[LGO] Write: no effect. Read: no line command active. Write: initiate line command indicated by bits 27-24. Read: line command active. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 329 NOTE: This bit stays set until the command completes. Writing zero has no effect. NOTE: This bit is shared with CLCR[LGO] Write: no effect. Read: no line command active. Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 330 The address/module assignment of the 16 subregions is device- specific. See the chip-specific LMEM information for these details. Some of the regions may not be used (non-cacheable), and some regions may not be capable of write-back. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 331 Controls the cache mode for region 4 Non-cacheable Non-cacheable Write-through Write-back 21–20 Region 5 mode Controls the cache mode for region 5 Non-cacheable Non-cacheable Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 332 Controls the cache mode for region 10 Non-cacheable Non-cacheable Write-through Write-back 9–8 Region 11 mode Controls the cache mode for region 11 Non-cacheable Non-cacheable Write-through Write-back Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 333 • Core master bus requests on the Processor Code (PC) bus, • Core master bus requests on the Processor System (PS) bus, and • SRAM controller requests from all other bus masters on the backdoor port. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 334 SRAM_L or the SRAM_U depending on their specific address. 14.4.2 SRAM Function 14.4.2.1 SRAM Configuration The figure below shows how the SRAM controller is configured. See chip-specific memory information for on-chip SRAM size details. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 335 • SRAM_U — Accessible by the system bus of the core and by the backdoor port. The backdoor port makes the SRAM accessible to the non-core bus masters (such as DMA). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 336 8 KB. The cache has 32-bit address and data paths and a 16-byte line size. The cache tags and data storage use single-port, synchronous RAMs. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 337 A cache set command is initiated by setting the CCR[GO] bit. This bit also acts as a busy bit for set commands. It stays set while the command is active and is cleared by the hardware when the set command completes. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 338 14.4.4.2 Cache line commands Cache line commands operate on a single line in the cache at a time. Cache line commands can be performed using a physical or cache address. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 339 A series of line commands with incremental cache addresses can be performed by just writing to the CLCR. • Place the command in CLCR[27:24], • Set the way (CLCR[WSEL]) and tag/data (CLCR[TDSEL]) controls as needed, Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 340 In general, if the valid indicator (CLCR[LCIVB] is cleared, the targeted line was invalid at the start of the line command and no line operation was performed. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 341 For line commands, CLCR[TDSEL] selects between tag and data. If the line command used a physical address and missed, the data is don't care. For write commands, the CCVR holds the write data. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 342 Functional Description Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 343 Miscellaneous System Control Module (MSCM). It specifically includes multiple views of the processor configuration; one that is available generically to the core and others that are available to any bus masters in the system. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 344 Processor 0 Configuration Register (MSCM_CP0CFG0) See section 15.3.11/352 4000_1034 Processor 0 Configuration Register (MSCM_CP0CFG1) See section 15.3.11/352 4000_1038 Processor 0 Configuration Register (MSCM_CP0CFG2) See section 15.3.11/352 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 345 This read-only field defines the processor personality for CPx if CPx = Cortex-M4, then PERSONALITY = 0x43_4D_34 (“CM4”). RYPZ Processor x Revision This read-only field defines the processor revision for CPx: 0x01 corresponds to the r0p1 core release. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 346 A privileged read from the CM4 returns the appropriate processor information. Reads from any other bus master return all zeroes. Attempted user mode or write accesses are terminated with an error. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 347 PCNT field: See bit field description MSCM_CPxCOUNT field descriptions Field Description 31–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 348 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 349 This read-only field defines the processor personality for CPx if CPx = Cortex-M4, then PERSONALITY = 0x43_4D_34 (“CM4”). RYPZ Processor x Revision This read-only field defines the processor revision for CPx: 0x01 corresponds to the r0p1 core release. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 350 A privileged read from the CA5 or the CM4 returns the appropriate processor information. Reads from any other bus master return all zeroes. Attempted user mode or write accesses are terminated with an error. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 351 PCNT field: See bit field description MSCM_CP0COUNT field descriptions Field Description 31–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 352 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 353 32 bits are terminated with an error. Address: 4000_1000h base + 400h offset + (4d × i), where i=0d to 3d OCMSZ OCMW Reserved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 354 25% of the address range, this bit is used. OCMEMn is a power-of-2 capacity. OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 355 OCMEM Memory Protection Unit. This read-only field identifies a memory protected by a Memory OCMPU Protection Unit. OCMEMn is not protected by an MPU. OCMEMn is protected by an MPU. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 356 OCMC0 OCMEM Control Field 0. This 4-bit field (if used) defines the configuration of the on-chip memory. The field’s functionality is dependent on the OCMT value. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 357 FAU is disabled. 16.1.3 External signal description The FAU has no external (off-chip) signals. 16.1.4 Functional description The FAU is a flash acceleration unit with flexible buffers for user configuration. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 358 3. Per 64-bit for Data Flash (bank 1), accessing the third longword requires 3 core clock cycles. The flash memory read itself takes 4 clocks, but the first clock overlaps with the second longword read. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 359 The FAU includes features designed to accelerate flash accesses. For more detailed information, refer to the FMC (same module as FAU) section in AN4745: Optimizing Performance on Kinetis K-series MCUs. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 360 Usage Guide Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 361 • FlexRAM for high-endurance data store or traditional RAM Flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 362 • Section programming for faster bulk programming times • Read access to the program flash block is possible while programming or erasing data in the data flash block or FlexRAM Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 363 • When configured for traditional RAM: • Read and write access possible to the FlexRAM while programming or erasing data in the program or data flash memory Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 364 Data flash sector — The data flash sector is the smallest portion of the data flash memory that can be erased. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 365 EEPROM, valid writes to the FlexRAM generates a new EEPROM backup data record stored in the EEPROM backup flash memory. FTFE Module — All flash blocks plus a flash management unit providing high-level control and an interface to MCU buses. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 366 Secure — An MCU state conveyed to the FTFE module as described in the Chip Configuration details for this device. In the secure state, reading and changing NVM contents is restricted. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 367 Register (FEPROT). 0x0_040D Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT). 0x0_040C Flash security byte. Refer to the description of the Flash Security Register (FSEC). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 368 The Program Once field can be read any number of times. This section of the program flash 0 IFR is accessed in 8 byte records using the Read Once command Program Once command. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 369 '1' = FlexRAM is loaded with valid EEPROM data during the flash reset sequence This read-only bitfield is reserved and each bit will always read as one. EEESPLIT Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 370 = Unimplemented or Reserved Table 17-4. FlexNVM partition code field description Field Description This read-only bitfield is reserved and must always be written as one. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 371 CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 372 Undefined 17.4.4.6/ 4002_0013 Program Flash Protection Registers (FTFE_FPROT0) Undefined 17.4.4.7/ 4002_0016 EEPROM Protection Register (FTFE_FEPROT) Undefined 17.4.4.8/ 4002_0017 Data Flash Protection Register (FTFE_FDPROT) Undefined Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 373 17.4.4.13/ 4002_002E Flash Error Status Register (FTFE_FERSTAT) 17.4.4.14/ 4002_002F Flash Error Configuration Register (FTFE_FERCNFG) 17.4.4.1 Flash Status Register (FTFE_FSTAT) The FSTAT register reports the operational status of the FTFE module. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 374 CCIF is set. Writing a 0 to the ACCERR bit has no effect. No access error detected Access error detected Flash Protection Violation Flag FPVIOL Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 375 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. Read Collision Error Interrupt Enable RDCOLLIE The RDCOLLIE bit controls interrupt generation when an FTFE read collision error occurs. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 376 During the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if the FlexNVM block is partitioned for EEPROM. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 377 Enables and disables mass erase capability of the FTFE module. When the SEC field is set to unsecure, the MEEN setting does not matter. Mass erase is enabled Mass erase is enabled Mass erase is disabled Mass erase is enabled Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 378 Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. Address: 4002_0000h base + 3h offset = 4002_0003h Read Write Reset * Notes: • x = Undefined at reset. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 379 This number is a reference to the FCCOB register name and is not the register address. FCCOB Number Typical Command Parameter Contents [7:0] FCMD (a code that defines the FTFE command) Flash address [23:16] Flash address [15:8] Flash address [7:0] Data Byte 0 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 380 Flash Configuration Field as indicated in the following table. Program flash protection register Flash Configuration Field offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 381 FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible if it contains any protected region. Program flash region is protected. Program flash region is not protected Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 382 Trying to alter data by writing to any protected area in the EEPROM results in a protection violation error and sets the FSTAT[FPVIOL] bit. EEPROM region is protected EEPROM region is not protected Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 383 (see the Erase Flash Block command description) is not possible if the data flash block contains any protected region or if the FlexNVM memory has been partitioned for EEPROM. Data Flash region is protected Data Flash region is not protected Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 384 Address: 4002_0000h base + 18h offset + (1d × i), where i=0d to 7d Read Write Reset * Notes: • x = Undefined at reset. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 385 0x03B7 0x03BF SACCL1 0x03B6 0x03BE SACCL2 0x03B5 0x03BD SACCL3 0x03B4 0x03BC Use the Program Once command to program the supervisor-only access control fields that are loaded during the reset sequence. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 386 The segment size is a fixed value based on the available program flash size divided by NUMSG. Flash Size Segment Size Segment Size Encoding 256 KBytes 4 KBytes 512 KBytes 8 KBytes 768 KBytes 16 KBytes Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 387 The NUMSG field indicates the number of equal-sized segments in the program flash. 0x20 32 segments 0x24 36 segments 0x28 40 segments 0x2C 44 segments 0x30 48 segments 0x38 56 segments 0x3C 60 segments 0x40 64 segments Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 388 The FDFD and DFDIE bits are readable and writable. The unassigned bits read 0 and are not writable. Address: 4002_0000h base + 2Fh offset = 4002_002Fh Read FDFD DFDIE Write Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 389 Individual regions within the flash memory can be protected from program and erase operations. Protection is controlled by the following registers: • FPROTn — Four registers protect 32 regions of the program flash memory as shown in the following figure Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 390 EEPROM backup Last FlexNVM address Figure 17-3. Data flash protection (2 data flash sizes) • FEPROT — Protects eight regions of the EEPROM memory as shown in the following figure Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 391 Access is controlled by the following registers: • FXACC — • eight registers control 64 segments of the program flash memory as shown in the following figure Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 392 Program flash size / 64 SACCH0[SA62] Program flash size / 64 SACCH0[SA63] Last program flash address Figure 17-6. Program flash supervisor access control 17.5.3 FlexNVM Description This section describes the FlexNVM memory. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 393 17-2). The remainder of the FlexRAM not used for EEPROM is not accessible while the FlexRAM is configured for EEPROM (see Set FlexRAM Function command). The EEPROM partition grows upward from the bottom of the FlexRAM address space. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 394 EEPROM data records is copied to the FlexRAM. After the CCIF bit is set, the FlexRAM is available for read or write access. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 395 • Writes_FlexRAM — minimum number of writes to each FlexRAM location • EEPROM — allocated FlexNVM based on DEPART; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 396 Table 17-5. FTFE Interrupt Sources FTFE Event Readable Interrupt Status Bit Enable Bit FTFE Command Complete FSTAT[CCIF] FCNFG[CCIE] FTFE Read Collision Error FSTAT[RDCOLERR] FCNFG[RDCOLLIE] Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 397 17.5.6 Flash memory reads and ignored writes The FTFE module requires only the flash address to execute a flash memory read. MCU read access is available to all flash memory. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 398 The FTFE command structure and operation are detailed in FTFE Command Operations. 17.5.9 FTFE Command Operations FTFE command operations are typically used to modify flash memory contents. The next sections describe: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 399 FSTAT are required to initiate the next command: the first write clears the error flags, the second write clears CCIF. 17.5.9.1.3 Command Execution and Error Reporting The command processing has several steps: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 400 FCCOB and FSTAT registers. 4. The FTFE sets the FSTAT[CCIF] bit signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 401 Program flash 0 Data flash FlexRAM Function 0x00 Read 1s Block × × Verify that a program flash or data flash block is erased. FlexNVM Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 402 IFR are erased then release MCU security. 0x41 Read Once Read 8 bytes of an indexed field in the program flash 0 IFR. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 403 0x4B Erase All Execute- Erase all program only Segments flash execute-only (XA) segments then release flash access control. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 404 FlexRAM Erase Erase Program Program Read Flash Read Flash Read E-Write R-Write Phrase Phrase Sector Sector Read Program Program Phrase flash Erase Flash Sector Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 405 The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 406 The FTFE may return invalid data to the MCU with the collision error flag (FSTAT[RDCOLERR]) set. When required by the command, address bit 23 selects between program flash memory (=0) and data flash memory (=1). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 407 Apply the 'Factory' margin to the normal read-1 level Table 17-9. Read 1s Block Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 408 If the FTFE fails to read all 1s (i.e. the flash section is not erased), the FSTAT(MGSTAT0) bit is set. The CCIF flag sets after the Read 1s Section operation completes. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 409 Program Check operation then reads the specified longword, and compares the actual read data to the expected data provided by the FCCOB. If the comparison at margin-1 fails, the MGSTAT0 bit is set. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 410 IFR, data flash IFR space, and the Version ID field. The Version ID field contains an 8 byte code that indicates a specific FTFE implementation. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 411 Command not available in current mode/security FSTAT[ACCERR] An invalid resource code is entered FSTAT[ACCERR] Flash address is out-of-range for the targeted resource. FSTAT[ACCERR] Flash address is not 64-bit aligned FSTAT[ACCERR] Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 412 The starting address must be 64-bit aligned (flash address [2:0] = 000): • Byte 0 data is written to the starting address ('start'), • Byte 1 data is programmed to byte address start+0b01, Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 413 (FDPROT) registers). If the erase verify fails, the MGSTAT0 bit in FSTAT is set. The CCIF flag will set after the Erase Flash Block operation has completed. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 414 Flash address is not 128-bit aligned for program flash, 64-bit aligned for data flash FSTAT[ACCERR] The selected program flash or data flash sector is protected FSTAT[FPVIOL] Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 415 Erase Flash Sector algorithm. The resume/suspend sequence runs indefinitely without completing the erase. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 416 Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 417 ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 17-11. Suspend and Resume of Erase Flash Sector Operation Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 418 After the Program Section operation has completed, the CCIF flag will set and normal access to the FlexRAM is restored. The contents of the Section Program Buffer are not changed by the Program Section operation. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 419 6. To program additional flash sectors, repeat steps through 5. 7. To restore EEPROM functionality, execute the Set FlexRAM Function command to make the FlexRAM available for EEPROM. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 420 Table 17-29. Read 1s All Blocks Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 421 Table 17-31. Read Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 422 Any errors have been encountered during the verify operation. FSTAT[MGSTAT0] 1. If a Program Once record is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command is allowed to execute again on that same record. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 423 Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 1. User margin read may be run using the Read 1s All Blocks command to verify all bits are erased. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 424 Key Byte 0 0x0_0003 Key Byte 1 0x0_0002 Key Byte 2 0x0_0001 Key Byte 3 0x0_0000 Key Byte 4 0x0_0007 Key Byte 5 0x0_0006 Key Byte 6 0x0_0005 Key Byte 7 0x0_0004 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 425 FSEC[SEC] field to the unsecure state, the security byte (see Flash configuration field description) is programmed to the unsecure state by the Erase All Blocks Unsecure command, and the Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 426 : • sets the read margin for 1s according to Table 17-41, • checks the contents of the program flash execute-only segments are in the erased state. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 427 Read 1s All Execute-only Segments command is executed and fails with the FSTAT[MGSTAT0] bit set. The Erase All Execute-only Segments command aborts if Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 428 FlexRAM load during reset option (only bit 0 used): 0 - FlexRAM loaded with valid EEPROM data during reset sequence 1 - FlexRAM not loaded during reset sequence Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 429 If erased, the Program Partition command erases the contents of the FlexNVM memory. If the FlexNVM is to be partitioned for EEPROM backup, the allocated EEPROM backup sectors are formatted for EEPROM use. Finally, the partition codes are Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 430 • When partitioned for EEPROM, the FlexRAM is typically used to store EEPROM data. Table 17-49. Set FlexRAM Function Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x81 (SETRAM) FlexRAM Function Control Code (see Table 17-50) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 431 FSTAT[ACCERR] FlexRAM Function Control Code is not defined FSTAT[ACCERR] FlexRAM Function Control Code is set to make the FlexRAM available for EEPROM, but FSTAT[ACCERR] FlexNVM is not partitioned for EEPROM Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 432 If the keys match, the FSEC[SEC] bits are changed to unsecure the MCU. The entire 8-byte key cannot be all 0s or all 1s, i.e. 0x0000_0000_0000_0000 and 0xFFFF_FFFF_FFFF_FFFF are not accepted by the Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 433 On each system reset the FTFE module executes a sequence which establishes initial values for the flash block configuration parameters, FPROT, FDPROT, FEPROT, FOPT, FSEC, FXACC, FSACC, FACSS, and FACSN registers and the FCNFG[RAMRDY, EEERDY] bits. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 434 • Using the Kinetis Family Enhanced EEPROM Functionality • Robust Over-the-Air Firmware Updates Using Program Flash Memory Swap on Kinetis Microcontrollers • Using the Kinetis Flash Execute-Only Access Control Feature Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 435 Various modules have module-specific clocks that can be generated from the FIRC_CLK, SIRC_CLK, SOSC_CLK, or SCGPLLCLK clock. In addition, there are various other module-specific clocks that have other alternate sources. While clock Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 436 (excluding WDOG, whose clock source with no DIVx). 18.3 Clock definitions The following table describes the clocks in the previous block diagram and other sections of this document. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 437 The following are a few of the more common clock configurations for this device: Option: High Speed RUN – (using the PLL from either the FIRC or SYS OSC) Clock Frequency CORE_CLK 168 MHz Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 438 48 MHz FLASH_CLK 24 MHz Option: Very Low Power RUN, VLPR (using the SIRC or SYS OSC) Clock Frequency CORE_CLK 4 MHz SYS_CLK 4 MHz BUS_CLK 4 MHz FLASH_CLK 1 MHz Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 439 Changes to clock source should be done when clock is gated by PCC to avoid glitches to output clock. 18.6 Module clocks The following table summarizes the clocks associated with each module. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 440 Max: BUS_CLK LPO_CLK, LPO_CLK: 128kHz SOSC_CLK, LPO_CLK LPO_CLK: 128kHz BUS_CLK Max: BUS_CLK BUS_CLK Max: BUS_CLK BUS_CLK, LPO_CLK Max: BUS_CLK Port Control BUS_CLK, LPO_CLK Max: BUS_CLK Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 441 18.6.2 EWM clocks This table shows the EWM clocks and the corresponding chip clocks. Table 18-2. EWM clock connections Module clock Chip clock Low Power Clock 128 kHz LPO Clock (LPO_CLK) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 442 ADCx module PCC module Peripheral Interface Clock PCC_ADCx[CGC] Registers PCC_ADCx[PCS]: see PCC chapter for PLLDIV2_CLK detailed setting DIV2 SOSCDIV2_CLK SOSC DIV2 ALTCLK1 SIRC SIRCDIV2_CLK ALTCLK2 DIV2 ALTCLK3 FIRCDIV2_CLK FIRC ALTCLK4 DIV2 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 443 The external clock are synchronized by FTM system clock (SYS_CLK). Therefore, to meet Nyquist criteria considering also jitter, the frequency of the external clock source must not exceed 1/4 of the system clock frequency. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 444 The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes. 18.6.8 RTC Clocking Information The following figure shows the input clock sources available for this module. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 445 The following figure shows the input clock sources available for this module. Peripheral Clocking - FlexCAN PCC module CANx module SCG module Peripheral Interface Clock BUS_CLK SCG DIVBUS PCC_FLEXCANx[CGC] Registers CANx_CTRL1[CLKSRC] SOSCDIV2_CLK SOSC DIV2 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 446 BUS_CLK SCG DIVBUS LPUARTx module PCC module Peripheral Interface Clock PCC_LPUARTx[CGC] Registers PCC_LPUARTx[PCS]: see PCC chapter for PLLDIV2_CLK detailed setting DIV2 SOSCDIV2_CLK SOSC DIV2 SIRC SIRCDIV2_CLK DIV2 FIRCDIV2_CLK FIRC DIV2 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 447 Clock Distribution chapter. 19.1.1.1.1 SCG clock mode transitions The following figure shows the valid clock mode transitions supported by SCG, for this device. For more information, see the Functional description section. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 448 The SCG can select either the output clock of the SPLL or a SCG reference clock (SIRC, FIRC, and SOSC) as the source for the MCU system clocks. The SCG also supports Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 449 • Clock monitor with reset and interrupt request capability for SPLL, SOSC, clocks • Lock detector with interrupt request capability for use with the SPLL • Each of the clock sources have reference dividers for clocking on-chip modules and peripherals, namely: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 450 Fast IRC Configuration Register (SCG_FIRCCFG) 0000_0000h 19.3.16/473 4006_430C Fast IRC Trim Configuration Register (SCG_FIRCTCFG) 0000_0000h 19.3.17/474 4006_4318 Fast IRC Status Register (SCG_FIRCSTAT) See section 19.3.18/475 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 451 Reference manual clocking chapter. SCG_PARAM field descriptions Field Description 31–27 Divider Present DIVPRES Indicates which system clock dividers are present in this instance of SCG. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 452 SCG_CSR field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 27–24 System Clock Source Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 453 Bus Clock Divide Ratio DIVBUS 0000 Divide-by-1 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 1000 Divide-by-9 1001 Divide-by-10 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 454 DIVSLOW Reset * Notes: • DIVCORE field: The reset value is controlled by user FOPT bits that get uploaded during reset. The two valid reset values are div-by-1 and div-by-2 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 455 This read-only field is reserved and always has the value 0. 7–4 Bus Clock Divide Ratio DIVBUS 0000 Divide-by-1 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 456 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 457 Reserved This read-only field is reserved and always has the value 0. 19–16 Core Clock Divide Ratio DIVCORE 0000 Divide-by-1 0001 Divide-by-2 0010 Divide-by-3 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 458 Divide-by-16 DIVSLOW Slow Clock Divide Ratio 0000 Reserved 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 1000 Reserved Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 459 0000 Reserved 0001 System OSC (SOSC_CLK) 0010 Slow IRC (SIRC_CLK) 0011 Fast IRC (FIRC_CLK) 0100 Reserved 0101 Reserved 0110 System PLL (SPLL_CLK) 0111 Reserved Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 460 Divide-by-10 1010 Divide-by-11 1011 Divide-by-12 1100 Divide-by-13 1101 Divide-by-14 1110 Divide-by-15 1111 Divide-by-16 DIVSLOW Slow Clock Divide Ratio 0000 Reserved 0001 Divide-by-2 0010 Divide-by-3 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 461 Fast IRC (FIRC_CLK) 0100 Reserved 0101 Reserved 0110 System PLL (SPLL_CLK) 0111 Reserved 1111 Reserved Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 462 This flag is reset on Chip POR only, software can also clear this flag by writing a logic one. System OSC Clock Monitor is disabled or has not detected an error System OSC Clock Monitor is enabled and detected an error Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 463 System OSC Stop Enable SOSCSTEN System OSC is disabled in Stop modes System OSC is enabled in Stop modes if SOSCEN=1. System OSC Enable SOSCEN Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 464 Clock divider 2 for System OSC. Used by modules that need an asynchronous clock source. Output disabled Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 465 This bit is reserved. Software should write 0 to this bit field. 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 466 OSC (SOSC) into the SCG, thus either the crystal oscillator or from an external clock input External reference clock selected Internal crystal oscillator of OSC selected. Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 467 Slow IRC is not enabled or clock is not valid Slow IRC is enabled and output clock is valid Lock Register This bit field can be cleared/set at any time. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 468 15–11 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 10–8 Slow IRC Clock Divide 2 SIRCDIV2 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 469 The SIRCCFG register cannot be changed when the slow IRC clock is enabled. When the slow IRC clock is enabled, writes to this register are ignored, and there is no transfer error. Address: 4006_4000h base + 208h offset = 4006_4208h Reset Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 470 Slow IRC low range clock (2 MHz) Slow IRC high range clock (8 MHz ) 19.3.14 Fast IRC Control Status Register (SCG_FIRCCSR) Address: 4006_4000h base + 300h offset = 4006_4300h Reset Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 471 System PLL is enabled in STOP mode, the Fast IRC will stay enabled even if FIRCSTEN=0. Fast IRC is enabled in Stop modes Fast IRC Enable FIRCEN Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 472 Fast IRC Clock Divide 1 Clock divider 1 for Fast IRC. Used to generate the clock source for modules that need an asynchronous clock source. Output disabled Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 473 This read-only field is reserved and always has the value 0. RANGE Frequency Range See chip-specific information for supported frequency ranges. Fast IRC is trimmed to 48 MHz Reserved Reserved Reserved Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 474 This read-only field is reserved and always has the value 0. TRIMSRC Trim Source Configures the external clock source to tune the Fast IRC. TRMSRC must be configured before programming FIRCSTAT register for trim update Reserved Reserved System OSC Reserved Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 475 FIRC is enabled and auto trimming is enabled (FIRCTREN=1 and FIRCTRUP=1), TRIMFINE register gets uploaded with the trimmed fine value. When FIRCTRUP=0, TRIMFINE bitfield is writeable, to allow user programming of fine trim values. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 476 System OSC is selected as its source and SOSCERR has set. System PLL Selected SPLLSEL System PLL is not the system clock source System PLL is the system clock source Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 477 As the device exits reset, the SCG_RCCR register should be configured as per the supported frequency ranges of the device BEFORE enabling the SPLL (SPLLEN =1). System PLL is disabled System PLL is enabled Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 478 Clock divider 1 for System PLL. Used to generate the clock source for modules that need an asynchronous clock source. Clock disabled Divide by 1 Divide by 2 Divide by 4 Divide by 8 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 479 Field Description 31–21 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 20–16 System PLL Multiplier MULT Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 480 Reserved This read-only field is reserved and always has the value 0. Clock Source SOURCE Configures the input clock source for the System PLL. System OSC (SOSC) Fast IRC (FIRC) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 481 SCG Modes FIRC SOSC SIRC High Speed Very Low Power HSRUN Valid SCG Modes VLPRUN Valid FIRC SCG Modes SIRC SOSC SOSC SIRC Figure 19-2. SCG Valid Mode Transition Diagram Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 482 Fast Internal Reference Clock (FIRC) mode is the default clock mode of operation and is entered Clock (FIRC) when all the following conditions occur: Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 483 • FIRCCSR[FIRCEN] = 1 • FIRCCSR[FIRCSTEN] = 1 SOSCLK is available in following low power stop modes (Normal Stop, VLPS) when all the below conditions are true. • SOSCCSR[SOSCEN] = 1 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 484 SPLLCLK is available in Normal Stop mode when all the following conditions are true: • SPLLCSR[SPLLEN] = 1 • SPLLCSR[SPLLSTEN] = 1 • SPLLSTEN control bit has no affect in VLPS Power mode. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 485 • Automatic Gain Control (AGC) to optimize power consumption The RTC oscillator operations are described in detail in Functional Description 20.1.2 Block Diagram The following is the block diagram of the RTC oscillator. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 486 20.2.1 EXTAL32 — Oscillator Input This signal is the analog input of the RTC oscillator. 20.2.2 XTAL32 — Oscillator Output This signal is the analog output of the RTC oscillator module. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 487 (hex) 4006_0000 RTC Oscillator Control Register (OSC32_CR) 20.4.1/487 20.4.1 RTC Oscillator Control Register (OSC32_CR) Address: 4006_0000h base + 0h offset = 4006_0000h Read ROSCSTB ROSCEREF ROSCSTPE ROSCEN Write Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 488 RTC digital core. The oscillator includes an internal feedback resistor of approximately 100 MΩ between EXTAL32 and XTAL32. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 489 Chapter 20 RTC Oscillator (OSC32) 20.6 Reset Overview There is no reset state associated with the RTC oscillator. 20.7 Interrupts The RTC oscillator does not generate any interrupts. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 490 Interrupts Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 491 Stop, Doze, and Debug signals. 21.2.1 Features The PCC module enables software to configure the following clocking options for each peripheral: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 492 Control and Config Registers Figure 21-1. PCC Clock Source Selection and Gating 21.3 Functional description The Peripheral Clock Control (PCC) module provides clock gating and clock source selection to each peripheral. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 493 PCC CAN1 (PCC_CAN1) 80000000h 40065098h PCC FLEXTMR3 (PCC_FLEXTMR3) 80000000h 4006509Ch PCC ADC1 (PCC_ADC1) C0000000h 400650B0h PCC LPSPI0 (PCC_LPSPI0) 80000000h 400650B4h PCC LPSPI1 (PCC_LPSPI1) 80000000h Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 494 400651B0h PCC LPUART2 (PCC_LPUART2) 80000000h 400651CCh PCC CMP0 (PCC_CMP0) 80000000h 400651D0h PCC CMP1 (PCC_CMP1) 80000000h 400651D4h PCC CMP2 (PCC_CMP2) 80000000h 21.4.1.2 PCC DMA0 (PCC_DMA0) 21.4.1.2.1 Address Register Offset PCC_DMA0 40065020h Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 495 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 496 1b - Peripheral is being used. Software cannot modify the existing clocking configuration. 28-27 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 497 Reserved Reset Bits Rese Reserved Reserved rved Reset 21.4.1.4.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 498 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.5 PCC DMAMUX0 (PCC_DMAMUX0) 21.4.1.5.1 Address Register Offset PCC_DMAMUX0 40065084h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 499 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 500 This read-only bit field is reserved and always has the value 0. — 26-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 501 Reset 21.4.1.7.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 502 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.8 PCC FLEXTMR3 (PCC_FLEXTMR3) 21.4.1.8.1 Address Register Offset PCC_FLEXTMR3 40065098h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 503 101b - Reserved. 110b - System PLL clock. 111b - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 504 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Control This read/write bit enables the clock for the peripheral. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 505 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.10 PCC LPSPI0 (PCC_LPSPI0) 21.4.1.10.1 Address Register Offset PCC_LPSPI0 400650B0h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 506 101b - Reserved. 110b - System PLL clock. 111b - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 507 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Control This read/write bit enables the clock for the peripheral. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 508 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.12 PCC PDB1 (PCC_PDB1) 21.4.1.12.1 Address Register Offset PCC_PDB1 400650C4h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 509 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 510 This read-only bit field is reserved and always has the value 0. — 26-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 511 Reset 21.4.1.14.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 512 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.15 PCC PDB0 (PCC_PDB0) 21.4.1.15.1 Address Register Offset PCC_PDB0 400650D8h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 513 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 514 1b - Peripheral is being used. Software cannot modify the existing clocking configuration. 28-27 This read-only bit field is reserved and always has the value 0. — 26-24 Peripheral Clock Source Select Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 515 This read-only bit field is reserved and always has the value 0. — 21.4.1.17 PCC FLEXTMR0 (PCC_FLEXTMR0) 21.4.1.17.1 Address Register Offset PCC_FLEXTMR0 400650E0h PCC Register 21.4.1.17.2 Diagram Bits INUS Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 516 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.18 PCC FLEXTMR1 (PCC_FLEXTMR1) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 517 This field can only be written when the CGC bit is 0 (clock disabled). Likewise, if the INUSE flag is set, this field is locked. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 518 This read-only bit field is reserved and always has the value 0. — 21.4.1.19 PCC FLEXTMR2 (PCC_FLEXTMR2) 21.4.1.19.1 Address Register Offset PCC_FLEXTMR2 400650E8h PCC Register 21.4.1.19.2 Diagram Bits INUS Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 519 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.20 PCC ADC0 (PCC_ADC0) 21.4.1.20.1 Address Register Offset PCC_ADC0 400650ECh Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 520 000b - Clock is off . 001b - System Oscillator Bus Clock. 010b - Slow IRC Clock. 011b - Fast IRC Clock. 100b - Reserved. 101b - Reserved. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 521 Reset 21.4.1.21.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 522 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.22 PCC RTC (PCC_RTC) 21.4.1.22.1 Address Register Offset PCC_RTC 400650F4h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 523 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 524 This read-only bit field is reserved and always has the value 0. — 26-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 525 Reset 21.4.1.24.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 526 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.25 PCC PORTA (PCC_PORTA) 21.4.1.25.1 Address Register Offset PCC_PORTA 40065124h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 527 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 528 This read-only bit field is reserved and always has the value 0. — 26-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 529 Reset 21.4.1.27.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 530 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.28 PCC PORTD (PCC_PORTD) 21.4.1.28.1 Address Register Offset PCC_PORTD 40065130h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 531 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 532 This read-only bit field is reserved and always has the value 0. — 26-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 533 Reset 21.4.1.30.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 534 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.31 PCC FLEXIO (PCC_FLEXIO) 21.4.1.31.1 Address Register Offset PCC_FLEXIO 40065168h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 535 101b - Reserved. 110b - System PLL clock. 111b - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 536 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Control Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 537 This read-only bit field is reserved and always has the value 0. — 21.4.1.33 PCC EWM (PCC_EWM) 21.4.1.33.1 Address Register Offset PCC_EWM 40065184h PCC Register 21.4.1.33.2 Diagram Bits INUS Reserved Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 538 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.34 PCC LPI2C0 (PCC_LPI2C0) 21.4.1.34.1 Address Register Offset PCC_LPI2C0 40065198h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 539 101b - Reserved. 110b - System PLL clock. 111b - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 540 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Control This read/write bit enables the clock for the peripheral. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 541 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.36 PCC LPUART0 (PCC_LPUART0) 21.4.1.36.1 Address Register Offset PCC_LPUART0 400651A8h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 542 101b - Reserved. 110b - System PLL clock. 111b - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 543 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Control This read/write bit enables the clock for the peripheral. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 544 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.38 PCC LPUART2 (PCC_LPUART2) 21.4.1.38.1 Address Register Offset PCC_LPUART2 400651B0h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 545 101b - Reserved. 110b - System PLL clock. 111b - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 546 This bit shows whether the peripheral is present on this device. 0b - Peripheral is not present. 1b - Peripheral is present. Clock Control This read/write bit enables the clock for the peripheral. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 547 This read-only bit field is reserved and always has the value 0. — 21.4.1.40 PCC CMP1 (PCC_CMP1) 21.4.1.40.1 Address Register Offset PCC_CMP1 400651D0h PCC Register 21.4.1.40.2 Diagram Bits INUS Reserved Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 548 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 21.4.1.41 PCC CMP2 (PCC_CMP2) 21.4.1.41.1 Address Register Offset PCC_CMP2 400651D4h PCC Register Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 549 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 550 Memory map and register definition Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 551 The MCU exits reset in functional mode where the CPU is executing code. See Boot options for more details. The following figure shows a block diagram of the reset sources for this device. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 552 System reset begins with the on-chip regulator in full regulation and system clocking generation from an internal reference. When the processor exits reset, it performs the following: • Reads the start SP (SP_main) from vector-table offset 0 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 553 The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a transition from low to high or high to low. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 554 VLPR and VLPW. 22.2.2.5 Loss-of-lock (LOL) reset The SCG module contains a loss-of-lock detector, to indicate a reset has been caused by a loss of lock in the SCG PLL/FLL. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 555 Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the rest of the chip comes out of system reset. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 556 After flash initialization has completed, the RESET_b pin is released, and the internal Chip Reset negates after the RESET_b pin is pulled high. Keeping the RESET_b pin asserted externally delays the negation of the internal Chip Reset. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 557 CDBGRSTREQ does not reset the debug-related registers within the following modules: • CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR) • FPB • DWT • ITM • NVIC • Crossbar bus switch Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 558 POR ramp where the device drives the pin low prior to establishing the Table continues on the next page... 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 559 Boot source can change between reset, but is always known before core reset negation. NMI input is disabled to platform when booting from ROM. FOPT section Reset Control Module for more detail options. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 560 NMI interrupt handler. 7. If FlexNVM is enabled, the flash controller continues to restore the FlexNVM data. This data is not available immediately out of reset and the system should not access Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 561 Flash reset 22~50us end system reset System reset release driving RESET pin Reset_b Core start ftfx initialization complete release core hold FOPT load IFR(include FOPT) load Figure 22-2. Boot Sequence Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 562 Boot Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 563 LPSPI LPSPI0_PCS PTB5 LPSPI0_SOU PTB4 LPSPI0_SIN PTB3 LPSPI0_SCK PTB2 LPSPI1_PCS PTA6 LPSPI1_SOU PTD2 LPSPI1_SIN PTD1 LPSPI1_SCK PTD0 LPI2C LPI2C0_SCL PTA3 LPI2C0_SDA PTA2 LPI2C1_SCL PTE1 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 564 PC or an embedded host communicating with the Kinetis Bootloader. Regardless of the host/master (PC or embedded host), the Kinetis Bootloader always uses a command protocol to communicate with that host/master. Commands are Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 565 FlashSecurityDisable Attempt to unlock flash security using the backdoor Supported GetProperty Get the current value of a property Supported Reset Reset the chip Supported Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 566 The Kinetis Bootloader reads data from the Bootloader Configuration Area (BCA) to configure various features of the bootloader. The BCA resides in flash memory at offset 0x3C0, and provides all of the parameters needed to configure the Kinetis Bootloader Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 567 Inverted value of the divider to use for core and bus clocks when in high speed mode 0x1F pad byte 0x20 - 0x23 Reserved 0x24 - 0x27 Reserved Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 568 Table 23-4. clockFlags Configuration Field Flag Description HighSpeed Enable high speed mode (i.e., 48 MHz). Read Clock Configuration section for more information on the high speed mode. 1 - 7 Reserved Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 569 • If communication is detected, then all inactive peripherals are shut down, and the command phase is entered. NOTE The flash sector containing the vector table should not be located in the execute-only region, because the Kinetis Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 570 Was a Ping packet received on LPUARTn? Is direct boot valid? Is user application valid? Enable Timeout check and enable Timeout value Disable Timeout detection Figure 23-2. Kinetis Bootloader Start-up Flowchart Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 571 //!< Pointer to the bootloader's runtime context. const flash_driver_interface_t *flashDriver; //!< Flash driver API. const aes_driver_interface_t *aesDriver; //!< AES driver API. } bootloader_tree_t; The prototype of the entry point is: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 572 • If the data phase is incoming (from host to bootloader ), then the data phase is part of the original command. • If the data phase is outgoing (from bootloader to host), then the data phase is part of the response command. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 573 The protocol for a command with an incoming data phase contains: • Command packet (from host) • Generic response command packet (to host) • Incoming data packets (from host) • Generic response command packet (to host) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 574 • Data phases may be aborted by the receiving side by sending the final Generic Response early with a status of Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 575 The protocol for a command with an outgoing data phase contains: • Command packet (from host) • ReadMemory Response command packet (to host) (kCommandFlag_HasDataPhase set) • Outgoing data packets (to host) • Generic response command packet (to host) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 576 • If the ReadMemory Response command packet prior to the start of the data phase does not contain the kCommandFlag_HasDataPhase flag, then the data phase is aborted. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 577 A Ping packet must be sent before any other communications. In response to a Ping packet, the target sends a Ping Response packet. Table 23-5. Ping Packet Format Byte # Value Name 0x5A start byte 0xA6 ping Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 578 Byte # Value Parameter 0x5A start byte 0xA7 Ping response code Protocol bugfix Protocol minor Protocol major Protocol name = 'P' (0x50) Options low Options high CRC16 low CRC16 high Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 579 The framing packet contains a data packet payload. 0xA6 kFramingPacketType_Ping Sent to verify the other side is alive. Also used for UART autobaud. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 580 Table 23-12. Commands that are supported Command Name 0x01 FlashEraseAll 0x02 FlashEraseRegion 0x03 ReadMemory Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 581 ParameterCount: The number of parameters included in the command packet. Parameters: The parameters are word-length (32 bits). With the default maximum packet size of 32 bytes, a command packet can contain up to 7 parameters. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 582 GetProperty command. The GetPropertyResponse packet contains the framing packet data and the command packet data, with the command/response tag set to a GetPropertyResponse tag value (0xA7). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 583 • For a list of status codes returned by the Kinetis Bootloader in ROM, see Table 23-73, Kinetis Bootloader Status Error Codes. NOTE All the examples in this section depict byte traffic on serial peripherals that use framing packets. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 584 GenericResponse packet with a status code either set to kStatus_Success or an appropriate error status code. 23.3.8.2 Reset command The Reset command will result in bootloader resetting the chip. The Reset command requires no parameters. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 585 Each supported property has a unique 32-bit tag associated with it. The tag occupies the first parameter of the command packet. The target returns a GetPropertyResponse packet with the property values for the property identified with the tag in the GetProperty command. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 586 Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x08 0x00 crc16 0x73 0xD4 Command packet commandTag 0x07 – GetProperty flags 0x00 reserved 0x00 parameterCount 0x01 propertyTag 0x00000001 - CurrentVersion Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 587 The property tag and the new value to set are the 2 parameters required for the SetProperty command. Table 23-22. Parameters for SetProperty Command Byte # Command 0 - 3 Property tag 4 - 7 Property value Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 588 The SetProperty command has no data phase. Response: The target (Kinetis Bootloader) will return a GenericResponse packet with one of following status codes: Table 23-24. SetProperty Response Status Codes Status Code kStatus_Success kStatus_ReadOnly kStatus_UnknownProperty kStatus_InvalidArgument Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 589 0xC4 0x2E Command packet commandTag 0x01 - FlashEraseAll flags 0x00 reserved 0x00 parameterCount 0x00 MemoryID • If MemoryID = 0x00h, then internal flash. • If MemoryID = 0x01h, then QSPI0 memory. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 590 Generic Response 0x5A A4 0C 00 BA 55 A0 00 00 02 00 00 00 00 02 00 00 00 ACK: 0x5A A1 Figure 23-11. Protocol Sequence for FlashEraseRegion Command Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 591 FSEC byte in the flash configuration field at address 0x40C is programmed to 0xFE. However, if the mass erase enable option in the FSEC field is disabled, then the FlashEraseAllUnsecure command will fail. The FlashEraseAllUnsecure command requires no parameters. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 592 8-byte backdoor key (provided in the command) against the backdoor key stored in the flash configuration field (at address 0x400 in the flash). The backdoor low and high words are the only parameters required for FlashSecurityDisable command. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 593 0x43 0x7B Command packet commandTag 0x06 - FlashSecurityDisable flags 0x00 reserved 0x00 parameterCount 0x02 Backdoorkey_low 0x04 0x03 0x02 0x01 Backdoorkey_high 0x08 0x07 0x06 0x05 The FlashSecurityDisable command has no data phase. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 594 The start address and number of bytes are the 2 parameters required for WriteMemory command. Table 23-32. Parameters for WriteMemory Command Byte # Command 0 - 3 Start address 4 - 7 Byte count Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 595 Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x06 0x5A Command packet commandTag 0x04 - writeMemory flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x20000400 byteCount 0x00000064 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 596 Table 23-34. Parameters for read memory command Byte Parameter Description Start address Start address of memory to read from Byte count Number of bytes to read and return to caller Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 597 Value Framing packet Start byte 0x5A0xA4, packetType kFramingPacketType_Command length 0x0C 0x00 crc16 0x1D 0x23 Command packet commandTag 0x03 - readMemory flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x20000400 byteCount 0x00000064 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 598 The MCU ROM bootloader provides a flash driver API tree entry (flashDriver) that a user application can use to get the entry points for the whole flash API set that is supported by the bootloader. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 599 } B; uint32_t version; //!lt; combined version numbers } standard_version_t; //! @brief Interface for the flash driver. typedef struct FlashDriverInterface #if !defined(FLASH_API_TREE_1_0) standard_version_t version; //!lt; flash driver API version number. #endif Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 600 // pointer points to bootloader tree flash_config_t flash_config; // variable used to keep runtime state of flash driver // Get bootloader API tree from ROM tree = (bootloader_tree_t*)(*(uint32_t*)0x1c00001c); Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 601 • FlexNVM device: FlexNVM memory total size • non-FlexNVM device: unused EEpromTotalSize • FlexNVM device: the size (in bytes) of the EEPROM area that was partitioned from FlexRAM • non-FlexNVM device: unused prototype: flash_config_t Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 602 FLASH_Init must be always called before calling other API functions. Prototype: status_t FLASH_Init(flash_config_t *config); Table 23-37. Parameters Parameter Description config Pointer to flash_config_t data structure in memory, to store driver runtime state. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 603 Command is not available under current mode/ security. kStatus_FLASH_ProtectionViolation Any region of the program flash memory is protected. kStatus_FLASH_EraseKeyError Key is incorrect. kStatus_Success This function has performed successfully. Example: status_t status = FLASH_EraseAll(&flashInstance, kFLASH_ApiEraseKey); Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 604 Pointer to flash_config_t data structure in memory, to store driver runtime state. Start The start address of the desired flash memory to be erased. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 605 Pointer to the source buffer of data that is to be programmed into flash. lengthInBytes The length in bytes (not words or long words) to be erased; the length must also be word-aligned. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 606 Table 23-48. Returned value kFLASH_SecurityStateNotSecure Flash is under unsecured mode. kFLASH_SecurityStateBackdoorEnabled Flash is under secured mode and Backdoor is enabled. kFLASH_SecurityStateBackdoorDisabled Flash is under secured mode and Backdoor is disabled. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 607 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0xff 0xff 0xff 0xbf Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 608 Assume that flash_erase_all has been successfully executed. status_t status = flash_verify_erase_all (&flashInstance, kFLASH_MarginValueUser); NOTE For the choice of margin, see the FTFA chapter in the reference manual for detailed information. 23.4.5.9 FLASH_VerifyErase Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 609 The flash range to be verified is not fully erased. kStatus_Success This function has performed successfully. Example: Assume that flash region from 0x800 to 0xc00 has been successfully erased. status_t status = FLASH_VerifyErase(&flashInstance, 0x800, 1024, kFLASH_MarginValueUser); Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 610 The range to be verified is invalid. kStatus_FLASH_AccessError The following situation causes this response: 1. Command is not available under current mode/ security. 2. An invalid margin code is supplied. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 611 Get Flash Sector size kFLASH_PropertyPflashTotalSize Get total flash size kFLASH_PropertyPflashBlockBaseAddr Get flash base address kFLASH_PropertyPflashFacSupport Get FAC support status kFLASH_PropertyPflashAccessSegmentSize Get FAC segment size Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 612 Table 23-61. Parameters Parameter Description Config Pointer to flash_config_t data structure in memory, to store driver runtime state. Index Index for a certain Program Once Field. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 613 Reads a certain flash Program Once Field according to parameters passed by index and length. For targets that do not support FLASH_ReadOnce, the value of the FLASH_ReadOnce pointer is 0. Prototype: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 614 23.4.5.14 FLASH_ReadResource Reads certain regions of IFR determined by the start address, length, and option. For targets that do not support FLASH_ReadResource, the value of the FLASH_ReadResource pointer is 0. Prototype: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 615 23.4.5.15 FLASH_SetCallback Registers (like to write into a list) expected callback functions into the flash driver, for example, like a function that services a watchdog. Prototype: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 616 23-2) is enabled (tag field is filled with ‘kcfg’) and the i2cSlaveAddress field is filled with a value other than 0xFF. 0x10 is used as the default I2C slave address. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 617 Read 1 byte packet from target Read 1 byte 0x7A 0x5A Report Error received? received? from target Figure 23-16. Host reads ping response from target via I2C Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 618 Figure 23-18. Host reads response from target via I2C 23.5.2 SPI Peripheral The Kinetis Bootloader in ROM supports loading data into flash via the SPI peripheral, where the SPI peripheral serves as a SPI slave. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 619 "dummy" 0x00 bytes (which do not have framing packets). The following flowcharts demonstrate how the host reads a ping response, an ACK and a command response from target via SPI. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 620 Send 0x00 to 0x5A 0xA1 shift out 1 byte received? received? from target Report a Next action timeout error Figure 23-20. Host reads ACK from target via SPI Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 621 (8-bit data, no parity bit and 1 stop bit). If the bytes of the ping packet are sent one-by-one with more than 80 ms delay between them, then the autobaud Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 622 Reached Wait for 1 byte 0x5A 0xA1 maximum received? received? from target retries? Report a timeout error Figure 23-22. Host reads an ACK from target via UART Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 623 The Kinetis Bootloader in this device's ROM supports loading data into flash via the FlexCAN peripheral. It supports 5 predefined speeds on FlexCAN transferring: • 125 kHz • 250 kHz • 500 kHz Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 624 The following flow charts demonstrate the communication flow of how the host reads ping packet, ACK and response from the target. Figure 23-25. Host reads ping response from target via FlexCAN Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 625 Figure 23-26. Host reads ACK packet from target via FlexCAN Figure 23-27. Host reads a command response from target via FlexCAN 23.6 Get/SetProperty Command Properties This section lists the properties of the GetProperty and SetProperty commands. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 626 1 - Flash security is enabled UniqueDeviceId Unique device identification, value of Kinetis Unique Identification registers (16 for K series devices, 12 for KL series devices) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 627 CAN Slave SPI Slave I2C Slave UART If the peripheral is available, then the corresponding bit will be set in the property value. All reserved bits must be set to 0. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 628 • Set crcByteCount to the number of bytes to run the CRC check on, from the start address. • Set crcExpectedValue to the value that the CRC calculation should result in. Application integrity testing: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 629 A timeout occurred. kStatus_FlashSizeError Not used. kStatus_FlashAlignmentError Address or length does not meet required alignment. kStatus_FlashAddressError Address or length is outside addressable memory. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 630 CRC check is invalid, because the BCA is invalid or the CRC parameters are unset (all 0xFF bytes). kStatus_AppCrcCheckOutOfRange 10404 CRC check is valid but addresses are out of range. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 631 Information found here describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 632 24.3.1 Version ID Register (RCM_VERID) Address: 4007_F000h base + 0h offset = 4007_F000h MAJOR MINOR FEATURE Reset RCM_VERID field descriptions Field Description 31–24 Major Version Number MAJOR Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 633 MINOR This read only field returns the minor version number for the specification. FEATURE Feature Specification Number This read only field returns the feature set number. 0x0003 Standard feature set. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 634 31–17 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Existence of SRS[CORE1] status indication feature ECORE1 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 635 EWDOG This static bit states whether or not the feature is available on the device. The feature is not available. The feature is available. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 636 The reset value of this register depends on the reset source: • POR (including LVD) — 0x82 • LVD (without POR) — 0x02 • Other reset — a bit is set if its corresponding reset source caused the reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 637 Reset caused by peripheral failure to acknowledge attempt to enter stop mode This field is reserved. Reserved This read-only field is reserved and always has the value 0. MDM-AP System Reset Request MDM_AP Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 638 This read-only field is reserved and always has the value 0. Loss-of-Lock Reset Indicates a reset has been caused by a loss of lock in the SCG PLL/FLL. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 639 The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled. Address: 4007_F000h base + Ch offset = 4007_F00Ch Reset RSTFLTSR RSTFLTSEL Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 640 This register includes status flags to indicate the state of the mode pins during the last Chip Reset. Address: 4007_F000h base + 10h offset = 4007_F010h Reset BOOTROM Reset * Notes: • BOOTROM field: The reset state of this register depends on the boot mode. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 641 When either bit is set, will force boot from ROM during all subsequent system resets. No effect Force boot from ROM with RCM_MR[1] set. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 642 Software can clear the status flags by writing a logic one to a flag. Address: 4007_F000h base + 18h offset = 4007_F018h Reset Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 643 (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 644 (DELAY field) while an interrupt is generated. When an interrupt for a reset source is enabled, software has time to perform a graceful shutdown. A Chip POR source cannot be delayed by this feature. The SRS updates only after the system reset occurs. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 645 Software Interrupt Interrupt disabled. Interrupt enabled. Core Lockup Interrupt LOCKUP NOTE: The LOCKUP bit is useful only in devices with more than one core processor. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 646 Reset Delay Time Configures the maximum reset delay time from when the interrupt is asserted and the system reset occurs. 10 LPO cycles 34 LPO cycles 130 LPO cycles 514 LPO cycles Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 647 Following stated are general power modes, which are supported additionally by certain clocking mode options. Clock gating technique is used for general power modes and for the additional clocking mode options. Figure 25-1. Power Infrastructure Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 648 Wait) -via WFI voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 649 PCC peripheral control register to enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to the clock distribution and PCC chapters. 25.2.1.2 Compute Operation Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 650 PMC to handle the change in power consumption. This delay means the CPOACK bit is polled to determine when the AIPS peripheral space can be accessed without generating a bus error. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 651 In Stop mode, the bus clock is gated as core clock and system clock. This device supports a partial Stop mode that permits peripherals to run with the bus clock. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 652 During Compute Operation, a DMA wake-up will initiate a normal exit from Compute Operation. This includes enabling the clocks and negating the stop mode signal to the bus masters and bus slaves. The core clock always remains enabled during Compute Operation. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 653 5V domain is powered by VDD/VSS directly. It contains GPIO and PMC. VDDA Analog domain is powered by VDDA/VSSA. It contains analog modules such as ADC and CMP. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 654 The WFI instruction invokes wait and stop modes for the chip. The processor exits the low-power mode via an interrupt. The "Interrupt vector assignments" table in the Interrupts chapter describes interrupt operation and what peripherals can cause interrupts. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 655 VLPR and VLPW are limited in frequency. Any RESET VLPW HSRUN VLPR WAIT STOP VLPS Figure 25-2. Power mode state transition diagram NOTE Table 26-2 in the SMC chapter for more detailed mode transition conditions. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 656 Debug modules are discussed separately, see "Debug in low power modes" in the Debug chapter. Number ratings (such as 2 MHz and 1 Mbit/s) represent the maximum frequencies or maximum data rates per mode. Also, these terms are used: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 657 4 MHz max OFF in CPO Bus clock 4 MHz max 4 MHz max OFF in CPO FF in PSTOP2 Memory and memory interfaces Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 658 SIRC, FIRC and SOSC SIRC, FIRC and SOSC clocks only clocks only clocks only clocks only LS compare only LS compare only LS compare LS compare only Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 659 WAIT or VLPW mode. It can also be used to disable selected bus slaves immediately on entry into any stop mode (or Compute Operation), instead of waiting for Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 660 Functional in Stop mode Reset wakeup CAN stop wakeup Non-maskable interrupt 25.7 Power supply supervisor This device integrates the following power supervisor circuits: • Power-on reset (POR) • Low voltage detection (LVD) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 661 See PMC chapters for details. For more details on the POR/LVD reset and the LVW interrupt thresholds, see the electrical characteristics (LVR, LVD and POR) section in the Data Sheet. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 662 Power supply supervisor Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 663 This chapter describes all the available low-power modes, the sequence followed to enter/ exit each mode, and the functionality available while in each of the modes. The SMC is able to function during even the deepest low power modes. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 664 I/O states are held in all modes of operation. Several registers are used to configure the various modes of operation for the device. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 665 MCU enters the low power mode. Failure to do this may result in the low power mode not being entered correctly. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 666 This read only field returns the minor version number for the module specification. FEATURE Feature Specification Number This read only field returns the feature set number. 0x0000 Standard features implemented Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 667 ELLS2 This static bit states whether or not the feature is available on the device. The feature is not available. The feature is available. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 668 Chip Reset. It is unaffected by reset types that do not trigger Chip Reset. See the Reset section details for more information. Address: 4007_E000h base + 8h offset = 4007_E008h Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 669 (PMPROT) register. NOTE This register is reset on Chip POR and by reset types that trigger Chip POR. It is unaffected by reset types that do not Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 670 When in HSRUN mode, any reset clears RUNM and causes the system to exit to normal RUN mode after the MCU exits its reset flow. Normal Run mode (RUN) Reserved Very-Low-Power Run mode (VLPR) High Speed Run mode (HSRUN) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 671 This register is reset on Chip POR and by reset types that trigger Chip POR. It is unaffected by reset types that do not trigger Chip POR. See the Reset section details for more information. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 672 This bit is reserved for future expansion. Software should write 0 to this bit to maintain compatibility. Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 673 0000_0100 Current power mode is VLPR. 0000_1000 Current power mode is VLPW. 0001_0000 Current power mode is VLPS. 0010_0000 Reserved 0100_0000 Reserved 1000_0000 Current power mode is HSRUN 26.5 Functional description Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 674 Interrupt or Reset STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in Arm core. See note. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 675 PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of VLPS 26.5.2 Power mode entry/exit sequencing When entering or exiting low-power modes, the system must conform to an orderly sequence to manage transitions safely. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 676 Stop mode. 4. After all slaves have acknowledged they are ready to enter Stop mode, all system and bus clocks are gated off. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 677 Halted state when the debugger has been enabled. As part of this transition, system clocking is re-established and is equivalent to the normal RUN and VLPR mode clocking configuration. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 678 In addition, do not modify the clock source in the SCG module or any clock divider registers. Module clock enables in the PCC can be set, but not cleared. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 679 PMCTRL[RUNM] and causes the system to exit to normal RUN mode after the MCU exits its reset flow. 26.5.4 Wait modes This device contains two different wait modes which are listed here. • Wait • Very-Low Power Wait (VLPW) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 680 • a powered down CPU, with only I/O and a small register file retained, very few asynchronous mode peripherals operating, while the remainder of the MCU is powered down. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 681 In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR. A module capable of providing an asynchronous interrupt to the device takes the device out of VLPS and returns the device to VLPR mode. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 682 • the SCG-generated clock source is enabled, • all system clocks, except the core clock, are disabled, • the debug module has access to core registers, and • access to the on-chip peripherals is blocked. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 683 • Low voltage detect supporting two low voltage trip points (V and V ) and interrupt • Low power oscillator (LPO) with a typical frequency of 128 kHz 27.4 Modes of Operation Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 684 ). The LVWF bit is cleared by writing one to the LVWACK bit, but only if the internal supply has returned above the trip point; otherwise, the LVWF bit remains set. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 685 PMC_LVDSC2[LVWIE] bit. If enabled, an LVW interrupt request occurs when the LVWF is set. LVWF is cleared by writing one to the PMC_LVDSC2[LVWACK] bit, when the supply returns to above the trip point. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 686 When the internal voltage regulator is in low power mode, the LVD system is disabled, regardless of the PMC_LVDSC1 settings. Address: 4007_D000h base + 0h offset = 4007_D000h Read LVDF LVDIE LVDRE Write LVDACK Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 687 When the internal voltage regulator is in low power mode, the LVD system is disabled regardless of the PMC_LVDSC2 settings. Address: 4007_D000h base + 1h offset = 4007_D001h Read LVWF LVWIE Write LVWACK Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 688 NOTE: After disabling the LPO a time of 2 LPO clock cycles is required before it is allowed to enable it again. Violating this waiting time of 2 cycles can result in malfunction of the LPO. Low power oscillator enabled Low power oscillator disabled Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 689 This register contains the period trimming bits for the low power oscillator. Table 27-1. Trimming effect of LPOTRIM[4:0] LPOTRIM[4:0] Decimal Period of LPO clock 10000 –16 lowest 10001 –15 increasing 11110 –2 11111 –1 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 690 This read-only field is reserved and always has the value 0. LPOTRIM LPO trimming bits These bits are used for trimming the frequency of the low power oscillator. See the table above for trimming effect. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 691 MCU after presenting the correct backdoor key with Verify Backdoor Access Key command. The MEEN bit of FSEC byte can be used to disable the mass erase capability from debug port and the FlashEraseAllUnsecure command from ROM bootloader. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 692 FTFE chapter for more details. 28.3 Security hardware accelerators 28.3.1 CRC This device contain one cyclic redundancy check (CRC) module which can generates 16/32-bit CRC code for error detection. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 693 See the MPU chapter for more details. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 694 On-chip resource access control mechanism Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 695 • Independent LPO_CLK clock source • Programmable time-out period specified in terms of number of EWM LPO_CLK clock cycles. • Windowed refresh option • Provides robust check that program flow is faster than expected. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 696 EWM refresh instructions. 29.1.2.2 Wait Mode The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 697 Cell Reset to Enable Counter Reset EWM_CLKPRESCALER[CLK_DIV] EWM_CTRL[EWMEN] EWM Refreshed Counter overflow EWM Refresh EWM_CMPH[COMPAREH] EWM_out /EWM_out Output EWM_CMPL[COMPAREL] Control EWM_in Mechanism EWM Service Register Figure 29-1. EWM Block Diagram Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 698 INEN, ASSIN and EWMEN bits can be written once after a CPU reset. Modifying these bits more than once, generates a bus transfer error. Address: 4006_1000h base + 0h offset = 4006_1000h Read INTEN INEN ASSIN EWMEN Write Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 699 This fixed number of cycles is called EWM_refresh_time. 29.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to refresh the EWM counter. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 700 Field Description COMPAREH To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum refresh time is required. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 701 The EWM_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. For example, the EWM_out could be connected to the high voltage transistors circuits that control an AC motor in a large appliance. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 702 (setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted state prior to the CPU start refreshing the EWM. This ensures that the EWM_out stays in the deasserted state; otherwise, the EWM_out output signal is asserted. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 703 EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers for correct EWM refresh operation. Therefore, three possible conditions can occur: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 704 The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. 29.5 Usage Guide 29.5.1 EWM low-power modes This table shows the EWM low-power modes and the corresponding chip low-power modes. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 705 The following code segment shows the refresh write sequence of the EWM module. // Refresh EWM DisableInterrupts; // disable global interrupt EWM_SERV= 0xB4; // write the 1st refresh words EWM_SERV= 0x2C; // write the 2nd refresh words EnableInterrupts; // enable global interrupt Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 706 Usage Guide Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 707 Peripheral Interface Clock BUS_CLK SCG DIVBUS Registers WDOG_CS[CLK] LPO_CLK SOSC_CLK SOSC SIRC SIRC_CLK 30.1.2 WDOG low-power modes This table shows the WDOG low-power modes and the corresponding chip low-power modes. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 708 • Programmable 16-bit window value • Provides robust check that program flow is faster than expected • Early refresh attempts trigger a reset. • Optional timeout interrupt to allow post-processing diagnostics Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 709 SCG) 0xC520 128 Bus Cycle Control Status 16-bit Window Register Disable Protect Bit Write Control 0xD928 UPDATE PRES WIN Figure 30-1. WDOG block diagram 30.3 Memory map and register definition Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 710 DBG WAIT STOP Reset WDOG_CS field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 711 System oscillator clock (SOSC, from SCG) Slow internal reference clock (SIRC, from SCG) Watchdog Enable This write-once bit enables the watchdog counter to start counting. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 712 Stop Enable STOP This write-once bit enables the watchdog to operate when the chip is in stop mode. Watchdog disabled in chip stop mode. Watchdog enabled in chip stop mode. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 713 The watchdog counter (CNT) is continuously compared with the timeout value (TOVAL). If the counter reaches the timeout value, the watchdog forces a reset triggering event. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 714 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–8 High byte of Watchdog Window WINHIGH WINLOW Low byte of Watchdog Window Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 715 Pass through 125 ns–8.1925 ms Internal 8 MHz (SIRC) ÷256 32 µs–2.09728 s 1 MHz (from bus or external) Pass through 1 µs–65.54 ms Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 716 In addition, if window mode is used, software must not start the refresh sequence until after the time value set in the WIN register. See the following figure. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 717 The refresh write sequence can be • either two 16-bit writes ( 0xA602, 0xB480) or four 8-bit writes (0xA6, 0x02, 0xB4, 0x80) if WDOG_CS[CMD32EN] is 0; • one 32-bit write (0xB480_A602) if WDOG_CS[CMD32EN] is 1. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 718 • Conversely, if CS[UPDATE] remains 0, the only way to reconfigure the watchdog is by initiating a reset. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 719 WDOG logic loses its clock (the bus clock) and can no longer monitor the counter. If the watchdog counter overflows twice in succession (without an intervening reset), the backup reset function takes effect and generates a reset. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 720 (such as the bus clock) for the counter reference. On a power-on reset, the POR bit in the system reset register is set, indicating the user should perform the WDOG fast test. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 721 It is suggested to disable or reconfigure the watchdog at the very beginning of the software code, e.g. beginning of the startup or main function. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 722 Configure for reconfigurable DisableInterrupts; //disable global interrupt WDOG_CNT = 0xD928C520; //unlock watchdog while(WDOG_CS[ULK]==0); //wait until registers are unlocked WDOG_TOVAL = 256; //set timeout value WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) | Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 723 To refresh the watchdog and reset the watchdog counter to zero, a refresh sequence is required: DisableInterrupts; // disable global interrupt WDOG_CNT = 0xB480A602; // refresh watchdog EnableInterrupts; // enable global interrupt Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 724 Application Information Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 725 • Option for inversion of final CRC result • 32-bit CPU register programming interface 31.1.2 Block diagram The following is a block diagram of the CRC. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 726 Register name Access Reset value (in bits) page (hex) 4003_2000 CRC Data register (CRC_DATA) FFFF_FFFFh 31.2.1/727 4003_2004 CRC Polynomial register (CRC_GPOLY) 0000_1021h 31.2.2/728 4003_2008 CRC Control register (CRC_CTRL) 0000_0000h 31.2.3/728 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 727 When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 728 CRC calculation. A new CRC calculation is initialized by asserting CTRL[WAS] and then writing the seed into the CRC data register. Address: 4003_2000h base + 8h offset = 4003_2008h TOTR FXOR WAS Reset Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 729 Width of CRC protocol. TCRC 16-bit CRC protocol. 32-bit CRC protocol. Reserved This field is reserved. This read-only field is reserved and always has the value 0. 31.3 Functional description Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 730 8. When all values have been written, read the final CRC result from CRC_DATA[LU:LL]. Transpose and complement operations are performed on the fly while reading or writing values. See Transpose feature CRC result complement for details. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 731 CTRL[TOT] or CTRL[TOTR] fields, according to the CRC calculation being used. The following types of transpose functions are available for writing to and reading from the CRC data register: 1. CTRL[TOT] or CTRL[TOTR] is 00. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 732 = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 31-3. Transpose type 10 4. CTRL[TOT] or CTRL[TOTR] is 11. Bytes are transposed, but bits are not transposed. reg[31:0] becomes {reg[7:0], reg[15:8], reg[23:16], reg[31:24]} Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 733 The DATA register is written with MSB of data value first, thus the application with little-endian configured, the data write bytes transpose should be enabled when writing a 32bit value from variable to DATA register. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 734 -= sizeof(uint32_t); data = (uint8_t *)data32; // 8-bit reads and writes till end of data buffer while (dataSize) CRC_DATA = *data; data++; dataSize--; // read 32bit checksum result checksum32 = CRC_DATA; Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 735 // due to the transport option TOTR >= 2 // read 16bit checksum result from CRC_DATA[HU:HL] // otherwise, read checksum from CRC_DATA[LU:LL] checksum16 = (CRC_DATA & 0xFFFF0000) >> 16; Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 736 Usage Guide Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 737 • ARM Real-Time Trace Interface(1-pin asynchronous mode only) The basic Cortex-M4 debug architecture is very flexible. The following diagram shows the topology of the core debug architecture and its components. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 738 The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 739 Set HIGH to indicate an entry is present. Table 32-3. CM4 ROM table Component Address Value Notes NVIC 0xE00FF000 0xFFF0F003 Base address = Base address of ROM table + 0xFFF0F000 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 740 32.3.1 JTAG-to-SWD change sequence 1. Send more than 50 TCK cycles with TMS (SWDIO) =1 2. Send the 16-bit sequence on TMS (SWDIO) = 0111_1001_1110_0111 (MSB transmitted first) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 741 TAPs (TDO) are muxed based on the IR code which is selected. This design is fully JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset, ARM's IDCODE (IR=4'b1110) is selected. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 742 JTAG or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 32-6. MDM-AP Register Summary Address Register Description 0x0100_0000 Status MDM-AP Status Register Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 743 Table 32-7. MDM-AP Control register assignments Name Secure Description Flash Mass Erase in Progress Y Set to cause mass erase. Cleared by hardware after mass erase operation completes. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 744 Flash Ready Indicate Flash has been initialized and debugger can be configured even if system is continuing to be held in reset via the debugger. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 745 32.7 Debug Resets The debug system receives the following sources of reset: • JTAG_TRST_b from an external signal. This signal is optional and may not be available in all packages. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 746 IP even while system reset is asserted. While in system reset, access to other memory and register resources, accessed over the Crossbar Switch, is blocked. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 747 Macrocell (ITM) to a data stream, encapsulating IDs where required, that is then captured by a Trace Port Analyzer (TPA). The TPIU is specially designed for low-cost debug. 32.12 DWT The DWT is a unit that performs the following debug functionality: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 748 Note with the debug enabled, transitions from Run--> VLPR --> VLPS are still possible but also result in the system entering Stop mode instead. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 749 MDM-AP Control Register. In the case of a secure device that has mass erase disabled (FSEC[MEEN] = 10), attempts to mass erase via the debug interface are blocked. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 750 Debug and Security Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 751 Power-on reset Test Access Port (TAP) Controller 1-bit Bypass Register 32-bit Device Identification Register Boundary Scan Register TAP Instruction Decoder TAP Instruction Register Figure 33-1. JTAG (IEEE 1149.1) block diagram Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 752 • The TAP controller is forced into the Test-Logic-Reset state, thereby disabling the test logic and allowing normal operation of the on-chip system logic to continue unhindered • The instruction register is loaded with the IDCODE instruction Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 753 1. TDO output buffer enable is negated when the JTAGC is not in the Shift-IR or Shift-DR states. A weak pull may be implemented at the TDO pad for use when JTAGC is inactive. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 754 TDI while the TAP controller is in the Shift-IR state, and latched on the falling edge of TCK in the Update-IR state. The latched instruction value can only be changed in the Update-IR and Test-Logic-Reset TAP controller states. Synchronous entry into the Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 755 No action occurs in the Update-DR state. Part Revision Number Design Center Part Identification Number Reset Part Identification Number Manufacturer Identity Code Reset PIN (contd.) The following table describes the device identification register functions. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 756 The JTAGC block uses the IEEE 1149.1-2001 TAP for accessing registers. This port can be shared with other TAP controllers on the MCU. Ownership of the port is determined by the value of the currently loaded instruction. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 757 TCK signal. As the following figure shows, holding TMS at logic 1 while clocking TCK through a sufficient number of rising edges also causes the state machine to enter the Test-Logic-Reset state. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 758 Figure 33-4. IEEE 1149.1-2001 TAP controller finite state machine 33.4.3.1 Enabling the TAP controller The JTAGC TAP controller is enabled by setting the JTAGC enable to a logic 1 value. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 759 NOTE: Execution of this instruction asserts functional reset. Arm JTAG-DP Reserved 1010 This instruction goes the Arm JTAG-DP controller. See the Arm JTAG-DP documentation for more information. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 760 TCK in the Update-DR state. The data is applied to the external output pins by the EXTEST or CLAMP instruction. System operation is not affected. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 761 (the bypass register) while conducting an EXTEST type of instruction through the boundary scan register. CLAMP also asserts the internal system reset for the MCU to force a predictable internal state. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 762 To initialize the JTAGC block and enable access to registers, the following sequence is required: 1. Place the JTAGC in reset through TAP controller state machine transitions controlled by TMS 2. Load the appropriate instruction for the test or action to be performed Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 763 PTB0 can be sampled by both ADC0 and ADC1. The interleaved mode is enabled by SIM_CHIPCTL[ADC_INTERLEAVE_EN] bits. For more information, see "ADC Hardware Interleaved Channels" in the ADC chapter of Reference Manual. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 764 RTC_CLKOUT PTE8 ACMP0_IN3 ACMP0_IN3 PTE8 FTM0_CH6 PTB5 DISABLED PTB5 FTM0_CH5 LPSPI0_PCS1 TRGMUX_IN0 ACMP1_OUT PTB4 ACMP1_IN2 ACMP1_IN2 PTB4 FTM0_CH4 LPSPI0_SOUT TRGMUX_IN1 PTC3 ADC0_SE11/ ADC0_SE11/ PTC3 FTM0_CH3 CAN0_TX ACMP0_IN4/ ACMP0_IN4/ EXTAL32 EXTAL32 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 765 PTC8 LPUART1_RX FTM1_FLT0 LPUART0_ PTA7 ADC0_SE3/ ADC0_SE3/ PTA7 FTM0_FLT2 RTC_CLKIN LPUART1_ ACMP1_IN1 ACMP1_IN1 PTA6 ADC0_SE2/ ADC0_SE2/ PTA6 FTM0_FLT1 LPSPI1_PCS1 LPUART1_ ACMP1_IN0 ACMP1_IN0 PTE7 ADC2_SE2/ ADC2_SE2/ PTE7 FTM0_CH7 FTM3_FLT0 ACMP2_IN6 ACMP2_IN6 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 766 DISABLED PTA11 FTM1_CH5 LPUART0_RX FXIO_D1 PTA10 JTAG_TDO/ PTA10 FTM1_CH4 LPUART0_TX FXIO_D0 JTAG_TDO/ noetm_Trace_ noetm_Trace_ PTE1 ADC2_SE6 ADC2_SE6 PTE1 LPSPI0_SIN LPI2C0_HREQ LPI2C1_SCL FTM1_FLT1 PTE0 ADC2_SE7 ADC2_SE7 PTE0 LPSPI0_SCK TCLK1 LPI2C1_SDA FTM1_FLT2 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 767 PTB7 Hi-Z — — — — PTB6 Hi-Z — — — — PTE14 Hi-Z — — — — PTE3 Hi-Z — — — — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 768 PTB1 Hi-Z — — — — PTB0 Hi-Z — — — — PTC9 Hi-Z — — — — PTC8 Hi-Z — — — — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 769 PTA11 Hi-Z — — — — PTA10 Hi-Z — — — — PTE1 Hi-Z — — — — PTE0 Hi-Z — — — — Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 770 The following figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous table of Pin Assignments. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 771 PTB16 VREFL PTB17 PTA17 PTB7 PTB6 PTE7 PTE14 PTA6 PTE3 PTA7 PTE12 PTC8 PTD17 PTC9 PTD16 PTB0 PTD15 PTB1 PTE9 PTC10 PTD14 PTC11 PTD13 Figure 34-1. 100 LQFP Pinout Diagram Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 772 34.3 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 773 EWM input for safety status of external safety circuits. The polarity of EWM_IN is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low. EWM_OUT_b EWM_out EWM reset out signal Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 774 Module signal Description name DAC0_OUT — DAC output Table 34-9. ACMPn Signal Descriptions Chip signal name Module signal Description name ACMPn_IN[ 6:0] IN[ 6:0] Analog voltage inputs ACMPn_OUT CMPO Comparator output Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 775 Table 34-14. LPSPIn Signal Descriptions Chip signal name Module signal Description name LPSPIn_SOUT SOUT Serial Data Out LPSPIn_SIN Serial Data In LPSPIn_SCK Serial Clock LPSPIn_PCS[3:0] PCS[3:0] Peripheral Chip Select 0-3 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 776 Table 34-18. GPIO Signal Descriptions Chip signal name Module signal Description name PTA[17:0] PORTA17–PORTA0 General-purpose input/output PTB[17:0] PORTB17–PORTB0 General-purpose input/output PTC[17:0] PORTC17–PORTC0 General-purpose input/output PTD[17:0] PORTD17–PORTD0 General-purpose input/output PTE[16:0] PORTE16–PORTE0 General-purpose input/output Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 777 ALT6 out en ALT7 out en ALT2 out data ALT3 out data ALT4 out data ALT5 out data ALT6 out data ALT7 out data ALT0 input/output (analog) Figure 35-1. Normal I/O structure Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 778 Disabled Disabled enable at reset Pin mux control Pin mux at reset PTA4/PTA5/ ALT0 PTC4/PTC5=ALT7; PTD3=ALT7; ALT0 PTA10=ALT7; Others=ALT0 Others=ALT0 Others=ALT0 Lock bit Interrupt and DMA request Digital glitch filter Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 779 • Pin interrupt is functional in all digital pin muxing modes • Digital input filter • Digital input filter for each pin, usable by any digital peripheral muxed onto the • Individual enable or bypass control field per pin Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 780 In Stop mode, the digital input filters are bypassed unless they are configured to run from the LPO clock source. 35.3.2.4 Debug mode In Debug mode, PORT operates normally. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 781 Pin Control Register n (PORTA_PCR0) See section 35.6.1/788 4004_9004 Pin Control Register n (PORTA_PCR1) See section 35.6.1/788 4004_9008 Pin Control Register n (PORTA_PCR2) See section 35.6.1/788 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 782 Interrupt Status Flag Register (PORTA_ISFR) 0000_0000h 35.6.4/792 4004_90C0 Digital Filter Enable Register (PORTA_DFER) 0000_0000h 35.6.5/792 4004_90C4 Digital Filter Clock Register (PORTA_DFCR) 0000_0000h 35.6.6/793 4004_90C8 Digital Filter Width Register (PORTA_DFWR) 0000_0000h 35.6.7/793 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 783 0000_0000h 35.6.2/791 reads 0) 4004_A084 Global Pin Control High Register (PORTB_GPCHR) (always 0000_0000h 35.6.3/791 reads 0) 4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR) 0000_0000h 35.6.4/792 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 784 See section 35.6.1/788 4004_B07C Pin Control Register n (PORTC_PCR31) See section 35.6.1/788 4004_B080 Global Pin Control Low Register (PORTC_GPCLR) (always 0000_0000h 35.6.2/791 reads 0) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 785 4004_C070 Pin Control Register n (PORTD_PCR28) See section 35.6.1/788 4004_C074 Pin Control Register n (PORTD_PCR29) See section 35.6.1/788 4004_C078 Pin Control Register n (PORTD_PCR30) See section 35.6.1/788 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 786 4004_D064 Pin Control Register n (PORTE_PCR25) See section 35.6.1/788 4004_D068 Pin Control Register n (PORTE_PCR26) See section 35.6.1/788 4004_D06C Pin Control Register n (PORTE_PCR27) See section 35.6.1/788 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 787 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 0000_0000h 35.6.4/792 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 0000_0000h 35.6.5/792 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 0000_0000h 35.6.6/793 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 0000_0000h 35.6.7/793 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 788 PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. • PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 789 The corresponding pin is configured in the following pin muxing slot as follows: Pin disabled (Alternative 0) (analog). Alternative 1 (GPIO). Alternative 2 (chip-specific). Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 790 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 791 Corresponding Pin Control Register is updated with the value in GPWD. GPWD Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 792 The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is reset to zero at system reset and whenever the digital filter is disabled. Each bit in the field enables the digital filter of the same number as the field. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 793 Digital filters are clocked by the LPO clock. 35.6.7 Digital Filter Width Register (PORTx_DFWR) The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C8h offset FILT Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 794 When locked, writes to the lower half of that pin control register are ignored, although a bus error is not generated on an attempted write to a locked register. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 795 • Interrupt disabled, default out of reset • Active high level sensitive interrupt • Active low level sensitive interrupt • Rising edge sensitive interrupt • Falling edge sensitive interrupt • Rising and falling edge sensitive interrupt Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 796 After a digital filter is enabled, the input is synchronized to the filter clock, either the bus clock or the LPO clock. If the synchronized input and the output of Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 797 The maximum latency through a digital filter equals three filter clock cycles plus the filter width configuration register. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 798 Functional description Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 799 36.2.1 Features Features of the GPIO module include: • Port Data Input register visible in all digital pin-multiplexing modes Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 800 See the chapter on signal multiplexing for the number of GPIO ports available in the device. 36.2.3.1 Detailed signal description Table 36-3. GPIO interface-detailed signal descriptions Signal Description PORTA31–PORTA0 General-purpose input/output Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 801 36.3.3/804 reads 0) 400F_F00C Port Toggle Output Register (GPIOA_PTOR) (always 0000_0000h 36.3.4/804 reads 0) 400F_F010 Port Data Input Register (GPIOA_PDIR) 0000_0000h 36.3.5/805 400F_F014 Port Data Direction Register (GPIOA_PDDR) 0000_0000h 36.3.6/805 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 802 0000_0000h 36.3.1/803 400F_F104 Port Set Output Register (GPIOE_PSOR) (always 0000_0000h 36.3.2/803 reads 0) 400F_F108 Port Clear Output Register (GPIOE_PCOR) (always 0000_0000h 36.3.3/804 reads 0) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 803 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 36.3.2 Port Set Output Register (GPIOx_PSOR) This register configures whether to set the fields of the PDOR. Address: Base address + 4h offset PTSO Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 804 Address: Base address + Ch offset PTTO Reset GPIOx_PTOR field descriptions Field Description PTTO Port Toggle Output Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 805 Pin logic level is logic 1. 36.3.6 Port Data Direction Register (GPIOx_PDDR) The PDDR configures the individual port pins for input or output. Address: Base address + 14h offset Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 806 To facilitate efficient bit manipulation on the general-purpose outputs, pin data set, pin data clear, and pin data toggle registers exist to allow one or more outputs within one port to be set, cleared, or toggled from a single register write. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 807 The corresponding Port Control and Interrupt module does not need to be enabled to update the state of the port data direction registers and port data output registers including the set/clear/toggle registers. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 808 Functional description Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 809 ADC0 ADC1 ADC2 1. This package for the product is not yet available. However, it is included in Package Your Way program for Kinetis MCU. Visit nxp.com/KPYW for more details. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 810 12-bit DAC output 11000 AD24 Reserved 11001 AD25 Reserved 11010 AD26 Temperature Sensor 11011 AD27 Bandgap (1V reference voltage) 11100 AD28 Reserved 11101 AD29 VREFH 11110 AD30 VREFL 11111 Module disabled None Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 811 12-bit DAC output 11000 AD24 Reserved 11001 AD25 Reserved 11010 AD26 Temperature Sensor 11011 AD27 Bandgap (1V reference voltage) 11100 AD28 Reserved 11101 AD29 VREFH 11110 AD30 VREFL 11111 Module disabled None Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 812 12-bit DAC output 11000 AD24 Reserved 11001 AD25 Reserved 11010 AD26 Temperature Sensor 11011 AD27 Bandgap (1V reference voltage) 11100 AD28 Reserved 11101 AD29 VREFH 11110 AD30 VREFL 11111 Module disabled None Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 813 DIV2 ALTCLK1 SIRC SIRCDIV2_CLK ALTCLK2 DIV2 ALTCLK3 FIRCDIV2_CLK FIRC ALTCLK4 DIV2 NOTE ALTCLK2~4 are not connected on this chip. 37.1.3 Inter-connectivity Information The ADC inter-connectivity is shown in following diagram. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 814 TRGMUX_PDBx_trig PDBx_DAC PDBx_Pulse PDBx_ADCx_trig PDBx_ADCx_pretrig0 PDBx_ADCx_pretrig1 PDBx_ADCx_pretrig2 PDBx PDBx_ADCx_pretrig3 PDBx_ADCx_pretrig4 PDBx_ADCx_pretrig5 PDBx_ADCx_pretrig6 PDBx_ADCx_pretrig7 ADCx_COCOH_TRG ADCx_COCOG_TRG ADCx_COCOF_TRG ADCx_COCOE_TRG ADCx_COCOD_TRG ADCx_COCOC_TRG ADCx ADCx_COCOB_TRG ADCx_COCOA_TRG ADCx_TRIGGER INTERRUPT ADCx_SEx DMA REQ 37.1.4 Application-related Information Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 815 • ADC1_SE8 and ADC2_SE8 channels are interleaved on PTB13 pin • ADC1_SE9 and ADC2_SE9 channels are interleaved on PTB14 pin PTB0 ADC0 PTB1 AD14 ADC1 AD15 Figure 37-1. ADC0 and ADC1 hardware interleaved channels integration Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 816 ALT2 also connected within the ADC module as ADC channel 27 ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC. Refer to REFSEL description in ADC chapter for more details. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 817 • SIM_ADCOPT[ADCxTRGSEL] bit is used to control the ADC triggering source/ scheme. • When ADCxTRGSEL=0, the ADC pre-trigger is coming from PDB directly. • When ADCxTRGSEL=1, the ADC pre-trigger is coming from TRGMUX, e.g. LPIT. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 818 ADC0 ADHWTS ports to control the channels. • The ADC0 COCO signals are directly feed-backed to PDB0 to deactivate the PDB lock state. Following are typical case for ADC triggering using PDB: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 819 ADC conversion. • With TRGMUX, a single LPIT could be used to trigger 3 ADCs at same time. This is one of the benefits for TRGMUX triggering, compared with PDB triggering. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 820 37.2.1 Features Following are the features of the ADC module: • Linear successive approximation algorithm with up to 12-bit resolution • Up to 16 single-ended external analog inputs • Output modes: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 821 • Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-Calibration mode 37.2.2 Block diagram The following figure is the ADC module block diagram. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 822 The ADC also requires four supply/reference/ground connections. NOTE For the number of channels supported on this device, see the chip-specific ADC information. The ADC does not produce any output signals. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 823 SC2[REFSEL]. The alternate voltage reference, V may select additional external pin ALTH or internal source depending on MCU configuration. See the chip configuration information on the Voltage References specific to this MCU. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 824 4002_7058 ADC Data Result Registers (ADC1_RE) 0000_0000h 37.4.4/833 4002_705C ADC Data Result Registers (ADC1_RF) 0000_0000h 37.4.4/833 4002_7060 ADC Data Result Registers (ADC1_RG) 0000_0000h 37.4.4/833 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 825 ADC Plus-Side General Calibration Offset Value Register 0 37.4.26/ 4002_70E0 0000_0000h (ADC1_CLP0_OFS) ADC Plus-Side General Calibration Offset Value Register X 37.4.27/ 4002_70E4 0000_0440h (ADC1_CLPX_OFS) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 826 0000_0004h 37.4.15/ 4003_B0B4 ADC General Calibration Value Register S (ADC0_CLPS) See section ADC Plus-Side General Calibration Value Register 3 37.4.16/ 4003_B0B8 See section (ADC0_CLP3) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 827 4003_C058 ADC Data Result Registers (ADC2_RE) 0000_0000h 37.4.4/833 4003_C05C ADC Data Result Registers (ADC2_RF) 0000_0000h 37.4.4/833 4003_C060 ADC Data Result Registers (ADC2_RG) 0000_0000h 37.4.4/833 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 828 ADC Plus-Side General Calibration Offset Value Register 0 37.4.26/ 4003_C0E0 0000_0000h (ADC2_CLP0_OFS) ADC Plus-Side General Calibration Offset Value Register X 37.4.27/ 4003_C0E4 0000_0440h (ADC2_CLPX_OFS) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 829 SC1B–SC1n registers do not initiate a new conversion. Address: Base address + 0h offset + (4d × i), where i=0d to 7d Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 830 Conversion complete interrupt is disabled. Conversion complete interrupt is enabled. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 831 11101 is selected as input. Voltage reference selected is determined by SC2[REFSEL]. REFSH 11110 is selected as input. Voltage reference selected is determined by SC2[REFSEL]. REFSL 11111 Module is disabled Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 832 Selects the input clock source to generate the internal clock, ADCK. See the clock distribution/clocking chapter of your device for details on which alternate clocks are supported. Alternate clock 1 (ADC_ALTCLK1) Alternate clock 2 (ADC_ALTCLK2) Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 833 Rn contains the result of an ADC conversion of the channel selected by the corresponding SC1A:SC1n. For every status and channel control register, there is a corresponding data result register. Unused bits in Rn are cleared. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 834 CVn fields that are related to the ADC mode of operation. CV2 is used only when the compare range function is enabled, that is, SC2[ACREN]=1. Address: Base address + 88h offset + (4d × i), where i=0d to 1d Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 835 This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 836 . This voltage may be additional external pin or internal ALTH source depending on the MCU configuration. See the chip configuration information for details specific to this MCU. Reserved Reserved Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 837 Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated. Hardware Average Enable AVGE Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 838 Rn. If the result is greater than the maximum or less than the minimum result value, it is forced to the appropriate limit for the current mode of operation. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 839 USR_OFS Reset ADCx_USR_OFS field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. USR_OFS USER Offset Error Correction Value Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 840 Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. YOFS Y offset error correction value 37.4.13 ADC Gain Register (ADCx_G) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 841 CLPx are automatically set when the self-calibration sequence is done, that is, CAL is cleared. If these registers are written by the user after calibration, the linearity error specifications may not be met. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 842 CLP3 field: Reset values are loaded out of IFR. ADCx_CLP3 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP3 Calibration Value Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 843 CLP1 field: Reset values are loaded out of IFR. ADCx_CLP1 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP1 Calibration Value Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 844 CLPX field: Reset values are loaded out of IFR. ADCx_CLPX field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 845 ADCx_CLP9 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved CLP9 Calibration Value Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 846 Reset ADCx_CLP3_OFS field descriptions Field Description 31–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP3_OFS CLP3 Offset Capacitor offset correction value Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 847 This read-only field is reserved and always has the value 0. CLP1_OFS CLP1 Offset Capacitor offset correction value 37.4.26 ADC Plus-Side General Calibration Offset Value Register 0 (ADCx_CLP0_OFS) Address: Base address + E0h offset CLP0_OFS Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 848 Reset ADCx_CLP9_OFS field descriptions Field Description 31–12 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP9_OFS CLP9 Offset Capacitor offset correction value Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 849 This clock source is then divided by a configurable value to generate the input clock ADCK, to the module. The clock is selected from one of the following sources by means of CFG1[ADICLK]. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 850 ADC continues to do conversions on the same SCn register that initiated the conversion. The hardware trigger function operates in conjunction with any of the conversion modes and configurations. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 851 • Low-power operation • Long sample time • Continuous conversion • Hardware average • Automatic compare of the conversion result to a software-determined compare value 37.5.4.1 Initiating conversions A conversion is initiated: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 852 37.5.4.2 Completing conversions A conversion is completed when the result of the conversion is transferred into the data result registers, Rn, as indicated in the following table. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 853 If the conversion was aborted by a reset, RA and Rn return to their reset states. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 854 The number of conversions is determined by the AVGS[1:0] bits, which can select 4, 8, 16, or 32 conversions to be averaged. While the hardware average function is in progress, SC2[ADACT] will be set. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 855 Inside range, inclusive Compare true if the result is greater than or equal to CV1 And the result is less than or equal equal to CV2. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 856 • Calibrate only one ADC instance at a time. So, when calibrating instance ADC0, the instances ADC1, ADC2, etc. are required to be idle. • Set ADCK (ADC clock) to half the maximum specified frequency. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 857 For example, in 8-bit single-ended mode, OFS[14:7] are subtracted from D[7:0]; OFS[15] indicates the sign (negative numbers are effectively added to the result) and OFS[6:0] are ignored. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 858 If a single conversion is selected and the compare trigger is not met, the ADC will return to its idle state and cannot wake the MCU from Wait mode unless a new conversion is initiated by the hardware trigger. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 859 2. Update CFG to select the input clock source and the divide ratio used to generate ADCK. 3. Update SC2 to select the conversion trigger, hardware or software, and compare function options, if enabled. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 860 // Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel. ADC_RA = 0xxx // Holds results of conversion. ADC_CV = 0xxx // Holds compare value when compare function enabled. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 861 • Set ADCK (ADC clock) to half the maximum specified frequency, e.g. 25 MHz. • Start ADC calibration by writing ADC_SC3 register with: CAL=1, AVGE=1, AVGS=11. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 862 37.6.6 ADC low-power modes The ADC will be available in STOP, VLPR, VLPW, and VLPS mode. NOTE When in VLPx mode, the ADC clock source is only limited to OSC and SIRC. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 863 This lock becomes inactive when receiving COCO signal from ADC. Figure 37-4. PWM Load Diagnosis – ADC Trigger Concept (block diagram) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 864 Usage Guide Figure 37-5. PWM Load Diagnosis – ADC Trigger Concept 1 (Timing) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 865 Not doing this can result in ADC conversion results with lower than specified accuracy. Calibration needs to be initiated manually by setting the CAL bit. For more details, please refer to "Calibration" section. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 866 Usage Guide Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 867 ACMP0_IN0 ACMP1_IN0 ACMP2_IN0 ACMP0_IN1 ACMP1_IN1 ACMP2_IN1 ACMP0_IN2 ACMP1_IN2 ACMP2_IN2 ACMP0_IN3 ACMP1_IN3 ACMP2_IN3 ACMP0_IN4 ACMP1_IN4 ACMP2_IN4 ACMP0_IN5 ACMP1_IN5 ACMP2_IN5 ACMP0_IN6 ACMP1_IN6 ACMP2_IN6 12-bit DAC output 12-bit DAC output 12-bit DAC output Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 868 Peripheral Clocking - CMP CMPn module PCC module SCG module Peripheral Interface Clock BUS_CLK SCG DIVBUS PCC_CMPn[CGC] Registers Main Clock (internal) 38.1.3 Inter-connectivity Information The CMP inter-connectivity is shown in following diagram. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 869 This device have an on-chip 12-bit DAC. The CMP also support reference from the output of 12-bit DAC. In case of 12-bit DAC output is used as CMP reference, it will occupy one of the external inputs (IN7) of the CMP module. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 870 The LPTMR only offers single wire trigger to CMP. And the configuration must be done by LPTMR itself (round robin) before entering low power mode. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 871 • Selectable inversion on comparator output • Capability to produce a wide range of outputs such as: • Sampled • Windowed, which is ideal for certain PWM zero-crossing-detection applications • Digitally filtered: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 872 • Option to route the output to internal comparator input 38.3.3 ANMUX key features The ANMUX has the following features: • Two 8-to-1 channel MUXes • Operational over the entire supply range Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 873 Reference Input 4 Reference Input 5 Sample input Reference Input 6 Reference Input 7 ANMUX Window and filter control CMPO From round-robin INNSEL[1:0] switch MSEL[2:0] Figure 38-1. CMP high level diagram Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 874 WINDOW=1 to generate COUTA. Sampling does NOT occur when WINDOW = 0. • The Filter block is bypassed when not in use. FILT_PER = 0x00 FILTER_CNT = 0x00 bypass_Filter_Block Figure 38-3. Filter block bypass logic Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 875 For such case, the software workaround is to configure the DAC side SEL[2:0] same as the non-DAC side, i.e. configuration of MSEL and PSEL register bits must be the same. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 876 Individual modes are discussed below. Table 38-3. Comparator sample/filter controls C0[FILTER_CN Mode # C0[EN] C0[WE] C0[SE] C0[FPR] Operation Disabled See the Disabled mode (# 0x00 Continuous Mode Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 877 Note Filtering and sampling settings must be changed only after setting C0[SE]=0, C0[FPR] =0 and C0[FILTER_CNT]=0x00. This resets the filter to a known state. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 878 The path from comparator input pins to output pin is operating in combinational unclocked mode. COUT and COUTA are identical. For control configurations that result in disabling the filter block, see Figure 38-3. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 879 #3B, the clock to filter block is internally derived. The comparator filter has no other function than sample/hold of the comparator output in this mode (# 3B). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 880 In Sampled, Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising edge is detected on the filter block clock input. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 881 CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1 Figure 38-8. Sampled, Filtered (# 4A): sampling point externally driven Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 882 WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 883 For control configurations which result in disabling the filter block, see Figure 38-3. When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 884 Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of C0[FILTER_CNT] must be 1. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 885 FILT_PER CGMUX clock SE=0 Figure 38-13. Windowed/Filtered mode The following figure shows the operation timing for this mode, considering uncertainty is introduced by the internal synchronization for the filter block. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 886 38.8.1/886 4007_5004 CMP Control Register 1 (CMP2_C1) 0000_0000h 38.8.2/890 4007_5008 CMP Control Register 2 (CMP2_C2) 0000_0000h 38.8.3/893 38.8.1 CMP Control Register 0 (CMPx_C0) Access: • Supervisor read/write • User read/write Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 887 Enables the CFR interrupt from the CMP. When this field is set, an interrupt will be asserted when CFR is set. Interrupt is disabled. Interrupt is enabled. Comparator Interrupt Enable Falling Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 888 Low Speed (LS) comparison mode is selected. High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 889 This read-only field is reserved and always has the value 0. Comparator hard block offset control. See chip data sheet to get the actual offset value with each level OFFSET Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 890 This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 891 If the same channel is selected as the reference voltage, this bit has no effect. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 892 INNSEL. Note: For the round robin mode of operation, the MSEL and PSEL bitfields in CMPx_C1 register must have different values. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 893 DACO range is from Vin/256 to Vin. 38.8.3 CMP Control Register 2 (CMPx_C2) Access: • Supervisor read/write • User read/write Address: Base address + 8h offset RRE RRIE FXMXCH Reset NSAM INITMOD ACOn Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 894 Channel 1 input changed flag. This bit is set if the channel 1 input changed from the last comparison with CH1F the fixed mux port. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 895 C0[CFF] is set on a falling edge, and C0[CFR] is set on a rising edge of the comparator output. The optionally filtered CMPO can be read directly through C0[COUT]. 38.9.1 Initialization A typical startup sequence is as follows. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 896 • Setting C0[FILTER_CNT] > 0x01 and • Setting C0[FPR] to a nonzero value or setting C0[SE]=1 If using the divided bus clock to drive the filter, it samples COUTA every C0[FPR] bus clock cycles. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 897 Table 38-4. Comparator sample/filter maximum latencies C0[E C0[W C0[S C0[FILTER_ Mode # Co[FPR] Operation Maximum latency CNT] Disabled 0x00 Continuous Mode 0x00 0x01 Sampled, Non-Filtered mode SAMPLE Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 898 DMA support is enabled by setting C0[DMAEN] and the interrupt is enabled by setting C0[IER], C0[IEF], or both, the corresponding change on COUT forces a DMA transfer request rather than a CPU interrupt instead. When the DMA has completed the transfer, it Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 899 Disabled mode, DACO is connected to the analog ground. DACEN VOSEL[7:0] VRSEL DACO Figure 38-15. 8-bit DAC block diagram 38.12.2 DAC resets This module has a single reset input, corresponding to the chip-wide peripheral reset. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 900 In programming the C2[INITMOD] registers, the INITMOD × round-robin clock period must be longer than the initialization delay, which can be referred from the chip datasheet. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 901 AC O n. T his will wake up MC U from s t op mode. Figure 38-16. Trigger mode Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 902 1. "x" means "do not care". 2. PSEL should not be set the same as MSEL. 3. Channel in the sweep side should not be the same as the fixed side. 38.14 Usage Guide Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 903 CMPx_C1 = (CMPx_C1 & ~(CMP_C1_ INPSEL_MASK | CMP_C1_PSEL_MASK)) | CMP_C1_INPSEL(1) | CMP_C1_PSEL(3); Then, the CMP output interrupts with their flags would be used to indicate the event of Zero Crossing Detection. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 904 This mode compares multiple input channels with the reference input channel (fixed) in a round-robin manner. It is commonly used to provide a trigger mode to wake up the MCU in STOP mode. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 905 All channel0~7 as the round robin checker channel in non-fixed port. The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. The initialization delay modulus is set to 64. Enable round robin mode. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 906 SoC. */ /* Set SoC enter into STOP mode. See the power management chapter. */ /* Change the voltage of input channel to wake up the SoC. */ Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 907 If the DAC and ADC use the same reference simultaneously, some degradation of ADC accuracy is to be expected due to DAC switching. 39.1.2 DAC Clocking Information The DAC clocking input is as below. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 908 Chip-specific information for this module Peripheral Clocking - DAC DAC0 module PCC module SCG module Peripheral Interface Clock BUS_CLK SCG DIVBUS PCC_DAC0[CGC] Registers 39.1.3 Inter-connectivity Information The DAC inter-connectivity is shown in following diagram. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 909 • On-chip programmable reference generator output. The voltage output range is from 1⁄4096 V to V , and the step is 1⁄4096 V , where V is the input voltage. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 910 • Static operation in Normal Stop mode • 16-word data buffer supported with configurable watermark and multiple operation modes • DMA support 39.4 Block diagram The block diagram of the DAC module is as follows: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 911 & DACBBIEN DACBFMD DACTRGSE Figure 39-1. DAC block diagram 39.5 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 912 When the DAC buffer is not enabled, this field controls the output voltage based on the following formula: * (1 + DAC_DATn[DATA0])/4096 When the DAC buffer is enabled, this field is mapped to the 16-word buffer. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 913 Address: 4003_F000h base + 20h offset = 4003_F020h DACBFRP DACBFUP DACBFWM DACBFMD Reset LPEN Reset DACx_STATCTRL field descriptions Field Description 31–28 DAC Buffer Read Pointer DACBFRP Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 914 Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 915 FIFO mode. The DAC buffer read pointer has not reached the watermark level. The DAC buffer read pointer has reached the watermark level. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 916 Scan mode or FIFO mode. When the buffer operation is switched from one mode to another, the read pointer does not change. The read pointer can be set to any value between 0 and STATCTRL[DACBFUP] by writing STATCTRL[DACBFRP]. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 917 (FIFO_SIZE-1), 32bit write will be ignored. NOTE: For 8bit write, address bit[0] determine which byte lane will be written to the FIFO according to little endian alignment. Only both byte lanes are written Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 918 If enabled, the DAC module continues to operate in Normal Stop mode and the output voltage will hold the value before stop. Stop mode In low-power stop modes, the DAC is fully shut down. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 919 The output of the DAC can be placed on an external pin or set as input to the analog comparator or ADC. CMP2 CMP1 CMP0 T-Gate T-Gate T-Gate DAC_buff_out DAC_no_buff_out ADC0 DAC_OUT 12-bit DAC Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 920 DMA request/ acknowledge signals based on watermark level settings. The FIFO depth implemented on this device is 16 words. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 921 For each PDB unit, there is only one trigger input from TRGMUX, but it supports different trigger sources. The internal trigger mux inside PDB is not used any more. PDB Trigger PDB Input 0000 TRGMUX_PDB0_EXTRG Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 922 • PDB0 channel 0 pre-trigger 5 acknowledgement input: ADC0SC1E_COCO • PDB0 channel 0 pre-trigger 6 acknowledgement input: ADC0SC1F_COCO • PDB0 channel 0 pre-trigger 7 acknowledgement input: ADC0SC1G_COCO The back-to-back chain diagram is as follows: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 923 PDB1 CH 0 PDB1 CH 0 pre-trigger 6 pre-trigger 2 PDB1 CH 0 PDB1 CH 0 pre-trigger 5 pre-trigger 3 PDB1 CH 0 pre-trigger 4 Figure 40-2. PDB1 back-to-back chain Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 924 PDB1 CH 0 pre-trigger 1 pre-trigger 6 PDB1 CH 0 PDB1 CH 0 pre-trigger 2 pre-trigger 5 PDB1 CH 0 PDB1 CH 0 pre-trigger 3 pre-trigger 4 Figure 40-4. PDB back-to-back chain Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 925 TRGMUX, which is then flexible to work as sample window for any CMP module. Table 40-1. PDB pulse-out enable register Register Module implementation Chip implementation PDBx_POEN 7:0 - POEN 0 - POEN[0] for CMP 31:8 - Reserved 31:1 - Reserved Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 926 • One channel flag and one sequence error flag per pre-trigger • DMA support • Up to 8 DAC interval triggers • One interval trigger output per DAC • One 16-bit delay interval register per DAC trigger output Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 927 For module to core output triggers implementation, see the chip configuration information. 40.2.3 Back-to-back acknowledgment connections PDB back-to-back operation acknowledgment connections are chip-specific. For implementation, see the chip configuration information. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 928 40.2.4 DAC External Trigger Input Connections The implementation of DAC external trigger inputs is chip-specific. See the chip configuration information for details. 40.2.5 Block diagram This diagram illustrates the major components of the PDB. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 929 In this diagram, only one PDB channel n, one DAC interval trigger x, and one Pulse-Out y are shown. The PDB-enabled control logic and the sequence error interrupt logic are not shown. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 930 If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. 40.4 Memory map and register definition Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 931 Channel n Delay 2 register (PDB2_CH0DLY2) 0000_0000h 40.4.9/940 40.4.10/ 4003_3024 Channel n Delay 3 register (PDB2_CH0DLY3) 0000_0000h 40.4.11/ 4003_3028 Channel n Delay 4 register (PDB2_CH0DLY4) 0000_0000h Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 932 DAC Interval Trigger n Control register (PDB0_DACINTC0) 0000_0000h 40.4.16/ 4003_6154 DAC Interval n register (PDB0_DACINT0) 0000_0000h 40.4.17/ 4003_6190 Pulse-Out n Enable register (PDB0_POEN) 0000_0000h 40.4.18/ 4003_6194 Pulse-Out n Delay register (PDB0_PO0DLY) 0000_0000h Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 933 Enables the PDB sequence error interrupt. When PDBEIE is set, any of the PDB channel sequence error flags generates a PDB sequence error interrupt. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 934 Trigger-In 11 is selected. 1100 Trigger-In 12 is selected. 1101 Trigger-In 13 is selected. 1110 Trigger-In 14 is selected. 1111 Software trigger is selected. PDB Enable PDBEN Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 935 • LDOK is automatically cleared when the values in the internal buffers are loaded into the registers or when PDBEN bit (PDB Enable) is cleared. • Writing 0 to LDOK has no effect. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 936 Address: Base address + 8h offset Reset PDBx_CNT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 937 Each PDB channel has one control register, CHnC1. The fields in this register control the functionality of each PDB channel operation. Address: Base address + 10h offset + (40d × i), where i=0d to 0d Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 938 PDB Channel Flags The CF[m] field is set when the PDB counter (PDB_CNT) matches the value CHnDLYm + 1. Write 0 to clear CF. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 939 Specifies the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading this field returns the value of internal register that is effective for the current PDB cycle. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 940 The value in this register's internal buffer is loaded into this register only after "1" is written to the SC[LDOK] bit. Address: Base address + 20h offset + (40d × i), where i=0d to 0d Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 941 These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective for the current PDB cycle. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 942 The value in this register's internal buffer is loaded into this register only after "1" is written to the SC[LDOK] bit. Address: Base address + 2Ch offset + (40d × i), where i=0d to 0d Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 943 These bits specify the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these bits returns the value of internal register that is effective for the current PDB cycle. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 944 Field Description 31–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. DAC External Trigger Input Enable Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 945 These bits specify the interval value for DAC interval trigger. DAC interval trigger triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT. Reading these bits returns the value of internal register that is effective for the current PDB cycle. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 946 These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when the PDB counter is equal to the DLY2. Reading these bits returns the value of internal register that is effective for the current PDB cycle. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 947 PDB channel n. The delays can be independently set using the channel delay registers (CHnDLYm), and the pre-triggers can be enabled or disabled using the PDB Channel Pre-Trigger Enables (CHnC1[EN[m]]). Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 948 ADC conversion finishes. • If the pre-trigger delay is 0 cycles, then both channels will flag a PDB channel sequence error and ADC will not perform a conversion. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 949 The DAC interval trigger pulse and the ADC pre-trigger/trigger pulses together allow precise timing of DAC updates and ADC measurements. This is outlined in the typical use case described in the following diagram. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 950 ADC pre-trigger/trigger outputs and Pulse-Out generation have the same time base, because they both share the PDB counter. The pulse-out connections implemented in this MCU are described in the device's chip configuration details. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 951 • PDB Modulus register (MOD) • PDB Interrupt Delay register (IDLY) • PDB Channel n Delay m register (CHnDLYm) Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 952 The following diagrams show the cases of the internal registers being updated with SC[LDMOD] is 00 and x1. CHnDLY1 CHnDLY0 PDB counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 40-9. Registers update with SC[LDMOD] = 00 Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 953 40.5.7 DMA If SC[DMAEN] is set, PDB can generate a DMA transfer request when SC[PDBIF] is set. When DMA is enabled, the PDB interrupt is not issued. 40.6 Application information Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 954 Therefore, use the lowest possible prescaler and multiplication factor for a given application. 40.7 Usage Guide 40.7.1 Using PDB to precisely control ADC conversion For detailed information, see the ADC trigger sections in the ADC chapter. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 955 FTM enhanced features • GTB_EN • Quadrature Decoder FTM3 • FTM enhanced features • GTB_EN 41.1.2 FTM Clocking Information The following figure shows the input clock sources available for this module. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 956 1/4 of the system clock frequency. 41.1.3 Inter-connectivity Information The FTM inter-connectivity is shown in the following diagram. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 957 • FTM0 FAULT2 = FTM0_FLT2 pin or TRGMUX output • FTM0 FAULT3 = FTM0_FLT3 pin • FTM1 FAULT0 = FTM1_FLT0 pin or TRGMUX output • FTM1 FAULT1 = FTM1_FLT1 pin or TRGMUX output Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 958 • FTM0 hardware trigger 2 = FTM0_FLT0 pin FTM1: • FTM1 hardware trigger 0 = TRGMUX trigger output • FTM1 hardware trigger 1 = SIM_FTMOPT1[FTM1SYNCBIT] • FTM1 hardware trigger 2 = FTM1_FLT0 pin FTM2: Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 959 The FlexTimer trigger outputs are also usually used as trigger source by other modules, for example, the above diagram shows a case of triggering PDB and ADC. See "Chip- specific Information" in PDB chapter and ADC Trigger Sources in ADC chapter for details. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 960 TPM module. Several key enhancements are made: • Signed up counter • Deadtime insertion hardware • Fault control inputs Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 961 • Selecting external clock connects FTM clock to a chip level input pin therefore allowing to synchronize the FTM counter with an off chip clock source • Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 • 16-bit counter Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 962 • Synchronized loading of write buffered FTM registers • Half cycle and Full cycle register reload capacity • Write protection for critical registers • Backwards compatible with TPM • Testing of input capture mode Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 963 The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable initial and final values and its counting can be up or up-down. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 964 7 input output mask, fault control and polarity control) CH7F channel 7 channel 7 interrupt CH7TRIG match trigger CH7IE Figure 41-1. FTM Block Diagram Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 965 This section presents a high-level summary of the FTM registers and how they are mapped. The registers and bits of an unavailable function in the FTM remain in the memory map and in the reset value, but they have no active function. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 966 41.4.6/979 4002_6040 Channel (n) Value (FTM3_C6V) 0000_0000h 41.4.7/981 4002_6044 Channel (n) Status And Control (FTM3_C7SC) 0000_0000h 41.4.6/979 4002_6048 Channel (n) Value (FTM3_C7V) 0000_0000h 41.4.7/981 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 967 4002_609C Half Cycle Register (FTM3_HCR) 0000_0000h 1020 41.4.29/ 4002_6200 Mirror of Modulo Value (FTM3_MOD_MIRROR) 0000_0000h 1020 41.4.30/ 4002_6204 Mirror of Channel (n) Match Value (FTM3_C0V_MIRROR) 0000_0000h 1021 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 968 Capture And Compare Status (FTM0_STATUS) 0000_0000h 41.4.9/982 41.4.10/ 4003_8054 Features Mode Selection (FTM0_MODE) 0000_0004h 41.4.11/ 4003_8058 Synchronization (FTM0_SYNC) 0000_0000h 41.4.12/ 4003_805C Initial State For Channels Output (FTM0_OUTINIT) 0000_0000h Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 969 0000_0000h 1021 41.4.30/ 4003_8210 Mirror of Channel (n) Match Value (FTM0_C3V_MIRROR) 0000_0000h 1021 41.4.30/ 4003_8214 Mirror of Channel (n) Match Value (FTM0_C4V_MIRROR) 0000_0000h 1021 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 970 Output Mask (FTM1_OUTMASK) 0000_0000h 41.4.14/ 4003_9064 Function For Linked Channels (FTM1_COMBINE) 0000_0000h 41.4.15/ 4003_9068 Deadtime Configuration (FTM1_DEADTIME) 0000_0000h 41.4.16/ 4003_906C FTM External Trigger (FTM1_EXTTRIG) 0000_0000h Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 971 1021 41.4.30/ 4003_9220 Mirror of Channel (n) Match Value (FTM1_C7V_MIRROR) 0000_0000h 1021 4003_A000 Status And Control (FTM2_SC) 0000_0000h 41.4.3/973 4003_A004 Counter (FTM2_CNT) 0000_0000h 41.4.4/977 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 972 41.4.18/ 4003_A074 Fault Mode Status (FTM2_FMS) 0000_0000h 1002 41.4.19/ 4003_A078 Input Capture Filter Control (FTM2_FILTER) 0000_0000h 1004 41.4.20/ 4003_A07C Fault Control (FTM2_FLTCTRL) 0000_0000h 1005 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 973 FTM configuration, clock source, filter prescaler, and prescaler factor. This register also contains the output enable control bits and the reload opportunity flag control. These controls relate to all channels within this module. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 974 0110 Divide by 7 0111 Divide by 8 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divide by 12 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 975 This bit enables the PWM channel output. This bit should be set to 0 (output disabled) when an input mode is used. Channel output port is disabled Channel output port is enabled Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 976 FTM counter operates in Up Counting mode. FTM counter operates in Up-Down Counting mode. 4–3 Clock Source Selection CLKS Selects one of the three FTM counter clock sources. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 977 Address: Base address + 4h offset COUNT Reset FTMx_CNT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. COUNT Counter Value Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 978 Address: Base address + 8h offset Reset FTMx_MOD field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Modulo Value Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 979 (n) filter is enabled) both them are inside the FTM. NOTE: The CHIS bit should be ignored when the channel (n) is not in an input mode. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 980 Used on the selection of the channel (n) mode. See Channel Modes. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 981 Captured FTM counter value of the input modes or the match value for the output modes 41.4.8 Counter Initial Value (FTMx_CNTIN) The Counter Initial Value register contains the initial value for the FTM counter. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 982 If another event occurs between the read and write operations, the write operation has no effect; therefore, CHF remains set indicating an event has occurred. In this case, a CHF interrupt request is not lost due to the clearing sequence for a previous CHF. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 983 Channel 5 Flag CH5F See the register description. No channel event has occurred. A channel event has occurred. Channel 4 Flag CH4F See the register description. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 984 • Capture Test mode • PWM synchronization • Write protection • Channel output initialization These controls relate to all channels within this module. Address: Base address + 54h offset Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 985 WPEN bit. WPDIS is cleared when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPDIS has no effect. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 986 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2 bits, is likely to result in unpredictable behavior. The synchronization event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF register) bits. See synchronization. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 987 0 input signal. Trigger is disabled. Trigger is enabled. Output Mask Synchronization SYNCHOM Selects when the OUTMASK register is updated with the value of its buffer. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 988 Reset Reset FTMx_OUTINIT field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 989 Channel 0 Output Initialization Value CH0OI Selects the value that is forced into the channel output when the initialization occurs. The initialization value is 0. The initialization value is 1. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 990 Channel output is masked. It is forced to its inactive state. Channel 5 Output Mask CH5OM Defines if the channel output is masked or unmasked. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 991 Defines if the channel output is masked or unmasked. Channel output is not masked. It continues to operate normally. Channel output is masked. It is forced to its inactive state. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 992 The deadtime insertion in this pair of channels is disabled. The deadtime insertion in this pair of channels is enabled. Dual Edge Capture Mode Captures For n = 6 DECAP3 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 993 Enables the capture of the FTM counter value according to the channel (n) input event and the configuration of the dual edge capture bits. This field applies only when DECAPEN = 1. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 994 DECAP bit is cleared automatically by hardware if Dual Edge Capture – One-Shot mode is selected and when the capture of channel (n+1) event is made. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 995 DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and when the capture of channel (n+1) event is made. The dual edge captures are inactive. The dual edge captures are active. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 996 This read-only field is reserved and always has the value 0. 7–6 Deadtime Prescaler Value DTPS Selects the division factor of the FTM input clock. This prescaled clock is used by the deadtime counter. Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 997 • Selects which channels are used in the generation of the channel triggers Several channels can be selected to generate multiple triggers in one PWM period. See External Trigger Initialization trigger Address: Base address + 6Ch offset Reset Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 998 Enables the generation of the trigger when the FTM counter is equal to the CNTIN register. The generation of initialization trigger is disabled. The generation of initialization trigger is enabled. Channel 1 Trigger Enable CH1TRIG Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 999 That is, the safe value of a channel is the value of its POL bit. Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 NXP Semiconductors...
Page 1000 This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high. The channel polarity is active low. Channel 2 Polarity POL2 Table continues on the next page... Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019 1000 NXP Semiconductors...

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