Table of Contents
Advertisement
Field
Configures the input source to be used in Pulse Counter mode. TPS must be altered only when the
LPTMR is disabled. The input connections vary by device. See the for information on the connections to
these inputs.
00
Pulse counter input 0 is selected.
01
Pulse counter input 1 is selected.
10
Pulse counter input 2 is selected.
11
Pulse counter input 3 is selected.
3
Timer Pin Polarity
TPP
Configures the polarity of the input source in Pulse Counter mode. TPP must be changed only when the
LPTMR is disabled.
0
Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
1
Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
2
Timer Free-Running Counter
TFC
When clear, TFC configures the CNR to reset whenever TCF is set. When set, TFC configures the CNR to
reset on overflow. TFC must be altered only when the LPTMR is disabled.
0
CNR is reset whenever TCF is set.
1
CNR is reset on overflow.
1
Timer Mode Select
TMS
Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is disabled.
0
Time Counter mode.
1
Pulse Counter mode.
0
Timer Enable
TEN
When TEN is clear, it resets the LPTMR internal logic, including the CNR and TCF. When TEN is set, the
LPTMR is enabled. While writing 1 to this field, CSR[5:1] must not be altered.
0
LPTMR is disabled and internal logic is reset.
1
LPTMR is enabled.
31.4.2 Low Power Timer Prescale Register (LPTMRx_PSR)
Address: 4004_0000h base + 4h offset = 4004_0004h
Bit
31
30
29
R
W
Reset
0
0
0
Bit
15
14
13
R
W
Reset
0
0
0
Freescale Semiconductor, Inc.
LPTMRx_CSR field descriptions (continued)
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 31 Low-Power Timer (LPTMR)
Description
24
23
22
21
0
0
0
0
0
8
7
6
5
PRESCALE
0
0
0
0
20
19
18
17
0
0
0
0
4
3
2
1
PBYP
PCS
0
0
0
0
16
0
0
0
505
Advertisement
Table of Contents
