Modes Of Operation; External Signal Description - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

• Two DWT comparators (addresses or address + data) provide programmable start/

stop recording

• CoreSight compliant debug functionality

43.1.3 Modes of operation

The MTB_RAM and MTB_DWT functions do not support any special modes of

operation. The MTB_RAM controller, as a memory-mapped device located on the

platform's slave AHB system bus, responds strictly on the basis of memory addresses for

accesses to its attached RAM array. The MTB private execution bus provides program

trace packet write information to the RAM controller. Both the MTB_RAM and

MTB_DWT modules are memory-mapped, so their programming models can be

All functionality associated with the MTB_RAM and MTB_DWT modules resides in the

core platform's clock domain; this includes its connections with the RAM array.

The MTB_RAM and MTB_DWT modules do not directly support any external

The internal interface includes a standard AHB bus with a 32-bit datapath width from the

appropriate crossbar slave port plus the private execution trace bus from the processor

core. The signals in the private execution trace bus are detailed in the following table

taken from the ARM CoreSight Micro Trace Buffer documentation. The signal direction

is defined as viewed by the MTB_RAM controller.

Table 43-1. Private execution trace port from the core to MTB_RAM

Freescale Semiconductor, Inc.

Indicates the processor is in the Lockup state. This signal is driven LOW for cycles

when the processor is executing normally and driven HIGH for every cycle the

processor is waiting in the Lockup state. This signal is valid on every cycle.

Indicates the next instruction address in execute, IAEX, is sequential, that is non-

IAEX register enable.

Registered address of the instruction in the execution stage, shifted right by one

bit, that is, PC >> 1.

Indicates the processor is performing non-instruction related activities.

Request for the processor to enter the Debug state, if enabled, and halt.

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 43 Micro Trace Buffer (MTB)