Spi Control Register 1 (Spix_C1) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

35.4.4 SPI Control Register 1 (SPIx_C1)

This read/write register includes the SPI enable control, interrupt enables, and
configuration options.
Address: Base address + 3h offset
Bit 7
Read
SPIE
Write
Reset
0
Field
7 SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO
SPIE (when FIFO is supported and enabled)
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): Enables the interrupt
for SPI receive buffer full (SPRF) and mode fault (MODF) events.
When the FIFO is supported and enabled (FIFOMODE is 1): This bit enables the SPI to interrupt the CPU
when the receive FIFO is full. An interrupt occurs when the SPRF bit is set or the MODF bit is set.
0 Interrupts from SPRF and MODF are inhibited—use polling (when FIFOMODE is not present or is 0)
or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)
1
Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or
Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)
6 SPI System Enable
SPE
Enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, the
SPI is disabled and forced into an idle state, and all status bits in the S register are reset.
0 SPI system inactive
1 SPI system enabled
5 SPI Transmit Interrupt Enable
SPTIE
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): This is the interrupt
enable bit for SPI transmit buffer empty (SPTEF). An interrupt occurs when the SPI transmit buffer is
empty (SPTEF is set).
When the FIFO is supported and enabled (FIFOMODE is 1): This is the interrupt enable bit for SPI
transmit FIFO empty (SPTEF). An interrupt occurs when the SPI transmit FIFO is empty (SPTEF is set).
0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested
4 Master/Slave Mode Select
MSTR
Selects master or slave mode operation.
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
Freescale Semiconductor, Inc.
6 5
SPE SPTIE
0 0
SPIx_C1 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 35 Serial Peripheral Interface (SPI)
4 3
MSTR CPOL
0 0
Description
2 1
CPHA SSOE LSBFE
1 0
0
0
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