Stop Mode; Table 20. Sleep-On-Exit Entry And Exit - ST STM32F40 Series Reference Manual

Power controller (PWR)
Table 20.
Sleep-on-exit
Mode entry
Mode exit
Wakeup latency
5.3.4

Stop mode

The Stop mode is based on the Cortex™-M4F deepsleep mode combined with peripheral
clock gating. The voltage regulator can be configured either in normal or low-power mode. In
Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI and the HSE RC
oscillators are disabled. Internal SRAM and register contents are preserved.
By setting the FPDS bit in the PWR_CR register, the Flash memory also enters power-down
mode when the device enters Stop mode. When the Flash memory is in power-down mode,
an additional startup delay is incurred when waking up from Stop mode (see
operating
Table 21.
Stop mode
STOP MR
( Main regulator)
STOP MR-FPD
STOP LP
STOP LP-FPD
Entering Stop mode
Refer to
To further reduce power consumption in Stop mode, the internal voltage regulator can be
put in low power mode. This is configured by the LPDS bit of the
register (PWR_CR) for STM32F405xx/07xx and STM32F415xx/17xx
control register (PWR_CR) for STM32F42xxx and
99/1422
Sleep-on-exit entry and exit
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex™-M4F System Control register.
Interrupt: refer to
STM32F415xx/17xx
STM32F43xxx
None
modes).
Stop operating modes
LPDS bit
0
0
1
1
Table 22 for details on how to enter the Stop mode.
Doc ID 018909 Rev 4
Description
Table 45: Vector table for STM32F405xx/07xx and
and Table 46: Vector table for STM32F42xxx and
FPDS bit
0
1
Flash wakeup time from Power Down
0
regulator wakeup time from LP mode
Flash wakeup time from Power Down
1
regulator wakeup time from LP mode
STM32F43xxx.
RM0090
Table 21: Stop
Wake-up latency
HSI RC startup time
HSI RC startup time +
mode
HSI RC startup time +
HSI RC startup time +
mode +
PWR power control
and PWR power