Stop Mode; Table 19. Bam-On-Exit Entry And Exit - ST STM32F423 Reference Manual

RM0430
Sleep-on-exit
Mode entry
Mode exit
Wakeup latency
Note: The BAM has been enhanced by adding SRAM2 that allows SRAM code to be executed
through the Ibus and Dbus, thus improving code execution performance.
5.3.5

Stop mode

The Stop mode is based on the Cortex
peripheral clock gating. The voltage regulator can be configured either in normal or low-
power mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI
and the HSE RC oscillators are disabled. Internal SRAM and register contents are
preserved.
Some settings in the PWR_CR register allow to further reduce the power consumption.
When the Flash memory is in power-down mode, an additional startup delay is incurred
when waking up from Stop mode (see
PWR power control register

Table 19. BAM-on-exit entry and exit

Set the Flash memory in low-power mode:
– FISSR/FMSSR and FPDS bits of the PWR_CR register
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
®
Refer to the Cortex -M4 with FPU System Control register.
Interrupt: refer to Table 40: Vector table for STM32F413/423
If Flash memory wakeup time is needed, FISSR/FMSSR bits of PWR_CR
register must be set
None when code executed from internal SRAM
Low-power mode Flash memory wakeup time, before restarting code
execution from Flash memory (refer to the Flash memory wakeup time in
the Electrical characteristics section of the datasheet).
®
-M4 with FPU deepsleep mode combined with
Table 20: Stop operating modes
(PWR_CR)).
RM0430 Rev 8
Power controller (PWR)
Description
and Section 5.4.1:
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