Stop Mode - ST STM32F207 Series Reference Manual

Power control (PWR)
4.3.4

Stop mode

The Stop mode is based on the Cortex
clock gating. The voltage regulator can be configured either in normal or low-power mode.
In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI and the HSE
RC oscillators are disabled. Internal SRAM and register contents are preserved.
By setting the FPDS bit in the PWR_CR register, the Flash memory also enters power down
mode when the device enters Stop mode. When the Flash memory is in power down mode,
an additional startup delay is incurred when waking up from Stop mode.
Entering Stop mode
The Stop mode is entered according to
SLEEPDEEP bit in the Cortex
Refer to
To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low-power mode. This is configured by the LPDS bit of the
(PWR_CR).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, the Stop mode entry is delayed until the APB
access is finished.
In Stop mode, the following features can be selected by programming individual control bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 17.3
•
Real-time clock (RTC): this is configured by the RTCEN bit in the
control register (RCC_BDCR)
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the
control & status register
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
RCC Backup domain control register
The ADC or DAC can also consume power during the Stop mode, unless they are disabled
before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit
in the DAC_CR register must both be written to 0.
If the application needs to disable the external clock before entering the stop mode, the
HSEON bit must be first disabled and the system clock switched on HSI.
Otherwise, if the HSEON bit is kept enabled while external clock ( external oscillator) can be
removed before entering stop mode, the clock security system (CSS) feature must be
enabled to detect any external oscillator failure and avoid a malfunction behavior when
entering stop mode.
74/1381
®
Table 10 for details on how to enter the Stop mode.
in Section 17: Independent watchdog
(RCC_CSR).
®
-M3 deepsleep mode combined with peripheral
Section : Entering low-power
-M3 System Control register is set.
(RCC_BDCR).
RM0033 Rev 9
mode, when the
PWR power control register
(IWDG).
RCC Backup domain
RM0033
RCC clock