Stop Mode; Table 9. Sleep-On-Exit - ST STM32F102 Series Reference Manual

Power control (PWR)
Table 9.
Sleep-on-exit
Mode entry
Mode exit
Wakeup latency
4.3.4

Stop mode

The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock
gating. The voltage regulator can be configured either in normal or low-power mode. In Stop
mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
oscillators are disabled. SRAM and register contents are preserved.
Entering Stop mode
Refer to
To further reduce power consumption in Stop mode, the internal voltage regulator can be
put in low-power mode. This is configured by the LPDS bit of the
(PWR_CR).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
In Stop mode, the following features can be selected by programming individual control bits:
●
Independent Watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 16.3
●
real-time clock (RTC): this is configured by the RTCEN bit in the
register (RCC_BDCR)
●
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the
register
●
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register
The ADC or DAC can also consume power during the Stop mode, unless they are disabled
before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit
in the DAC_CR register must both be written to 0.
Exiting Stop mode
Refer to
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.
54/690
Sleep-on-exit
WFI (wait for interrupt) while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
Refer to the Cortex™-M3 System Control register.
Interrupt: refer to
None
Table 10 for details on how to enter the Stop mode.
in Section 16: Independent watchdog
(RCC_CSR).
Table 10 for more details on how to exit Stop mode.
Description
Table 36: Vector table.
(IWDG).
(RCC_BDCR).
RM0008
Power control register
Backup domain control
Control/status