Samsung S3C2451X User Manual page 85

S3C2451X RISC MICROPROCESSOR
POWER SAVING MODE ENTERING/EXITING CONDITION
Table 2-8 shows that Power Saving mode state and Entering or Exiting condition. In general, the entering
conditions are set by the main CPU.
Pleas refer to power-related registers(PWRMODE, PWRCFG and WKUPSTAT) before apopting power saving
scheme on your system.
In dealing with sleep mode, It is good for you to know following two restrictions. To enter sleep mode by
BATT_FLT, you have to configure BATF_CFG bits of PWRCFG register. Not to exit from sleep mode when
BATT_FLT is LOW, you have to configure SLEEP_CFG bit of PWRCFG register.
Power down mode
Clock Gating at NORMAL
IDLE
STOP
SLEEP
Table 2-8. Power saving mode entering/exiting condition
Enter
Clear a respective clock
on/off bit for each IP to save
power.
CMD
CMD
CMD
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Exit
Set a respective clock on/off bit for each IP to
operate normally
1. All interrupt sources
2. RTC alarm
3. RTC Tick
4. BATT_FLT
1. EINT[15:0] (External Interrup)
2. RTC alarm
3. RTC Tick
4. BATT_FLT
1. EINT[15:0] (External Interrupt)
2. RTC alarm
3. RTC Tick
4. BATT_FLT
SYSTEM CONTROLLER
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