Samsung S3C2451X User Manual page 733

S3C2451X RISC MICROPROCESSOR
EXTCLK
XTIpll
Clock
Disable
VCO
Output
FCLK
Sleep mode is initiated.
Figure 29-7. Sleep Mode Return Oscillation Setting Timing
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Several slow clocks (XTIpll or EXTCLK)
ELECTRICAL DATA
Wake up from sleep mode
tOSC2
29-9