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PCM AUDIO INTERFACE
PCM_IRQ_STATn
TXFIFO_ERROR
_OVERFLOW
RXFIFO_EMPTY
RXFIFO_ALMOST
_EMPTY
RX_FIFO_FULL
RX_FIFO_ALMOST
_FULL
RXFIFO_ERROR
_STARVE
RXFIFO_ERROR
_OVERFLOW
NOTE:
More than one interrupt sources(which was set by PCM_IRQ_CTL register) can cause interrupt, at same
time(i.e, interrupt at PCM is OR-ed interrupt.) So in Interrupt Service Routine, user should check this
register bits which you set as interrupt sources.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
28-16
Specifications and information herein are subject to change without notice.
Bit
[6]
Interrupt is generated for TX FIFO overflow ERROR.
This occurs whenever the TX FIFO is written when it is already
full. This is considered as an ERROR and will have unexpected
results
1: IRQ is occurred.
0: IRQ is not occurred.
[5]
Interrupt is generated whenever the RX FIFO is empty
1: IRQ is occurred.
0: IRQ is not occurred.
[4]
Interrupt is generated whenever the RX FIFO is ALMOST
empty.
1: IRQ is occurred.
0: IRQ is not occurred.
[3]
Interrupt is generated whenever the RX FIFO is full
1: IRQ is occurred.
0: IRQ is not occurred.
[2]
Interrupt is generated whenever the RX FIFO is ALMOST full.
1: IRQ is occurred.
0: IRQ is not occurred.
[1]
Interrupt is generated for RX FIFO starve ERROR.
This occurs whenever the RX FIFO is read when it is still empty.
This is considered as an ERROR and will have unexpected
results
1: IRQ is occurred.
0: IRQ is not occurred.
[0]
Interrupt is generated for RX FIFO overflow ERROR.
This occurs whenever the RX FIFO is written when it is already
full. This is considered as an ERROR and will have unexpected
results
1: IRQ is occurred.
0: IRQ is not occurred.
S3C2451X RISC MICROPROCESSOR
Description
Initial State
0
0
0
0
0
0
0
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