Samsung S3C2451X User Manual page 510

HSMMC CONTROLLER
TIMEOUT CONTROL REGISTER
At the initialization of the Host Controller, the Host Driver shall set the Data Timeout Counter Value according to
the Capabilities register.
Register
TIMEOUTCON 0
TIMEOUTCON 1
Name Bit
Reserved
[7:4]
TIMEOU Data Timeout Counter Value
[3:0]
TCON
Refer to the Data Timeout Error in the Error Interrupt Status register for
information on factors that dictate timeout generation. Timeout clock frequency
will be generated by dividing the base clock SDCLK value by this value. When
setting this register, prevent inadvertent timeout events by clearing the Data
Timeout Error Status Enable (in the Error Interrupt Status Enable register)
SOFTWARE RESET REGISTER
A reset pulse is generated when writing 1 to each bit of this register. After completing the reset, the Host
Controller shall clear each bit. Because it takes some time to complete software reset, the SD Host Driver shall
confirm that these bits are 0.
Register
SWRST0
SWRST1
Name Bit
[7:3]
Reserved
Software Reset For DAT Line
RSTDAT [2]
Only part of data circuit is reset. DMA circuit is also reset. (RWAC)
The following registers and bits are cleared by this bit:
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-42
Specifications and information herein are subject to change without notice.
Address
0X4AC0002E
0X4A80002E
This value determines the interval by which DAT line timeouts are detected.
1111b Reserved
27
1110b SDCLK x 2
26
1101b SDCLK x 2
.............. ...
14
0001b SDCLK x 2
13
0000b SDCLK x 2
Address
0X4AC0002F
0X4A80002F
Present State register
Buffer Read Enable
Buffer Write Enable
Read Transfer Active
Write Transfer Active
DAT Line Active
Command Inhibit (DAT)
R/W
R/W Timeout Control Register (Channel 0)
R/W Timeout Control Register (Channel 1)
Description
R/W
R/W Software Reset Register (Channel 0)
R/W Software Reset Register (Channel 1)
Description
S3C2451X RISC MICROPROCESSOR
Description
Description
Reset Value
0x0
0x0
Initial
Value
0
0
Reset Value
0x0
0x0
Initial
Value
0
0