Samsung S3C2451X User Manual page 472

HSMMC CONTROLLER
SD CLOCK SUPPLY SEQUENCE
The sequence for supplying SD Clock to a SD card is described in Figure 21-3. The clock shall be supplied to the
card before either of the following actions is taken.
a) Issuing a SD command
b) Detect an interrupt from a SD card in 4-bit mode.
(1) Calculate a divisor to determine SD Clock frequency by reading Base Clock Frequency for SD Clock in the
Capabilities register. If Base Clock Frequency for SD Clock is 00 0000b, the Host System shall provide this
information to the Host Driver by another method.
(2) Set Internal Clock Enable(ENINTCLK) and SDCLK Frequency Select in the Clock Control register in
accordance with the calculated result of step (1).
(3) Check Internal Clock Stable(STBLINTCLK) in the Clock Control register. Repeat this step until Clock Stable is
1.
(4) Set SD Clock Enable(ENSDCLK) in the Clock Control register to 1. Then, the Host Controller starts to supply
the SD Clock.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-4
Specifications and information herein are subject to change without notice.
START
(1)
Calculate a divisor for SD Clock frequency
(2)
Set SDCLK frequency select and
Internal Clock Enable
(3)
Check Internal Clock
Enable
(4)
Set SD Clock ON
End
Figure 21-3SD Clock Supply Sequence
S3C2451X RISC MICROPROCESSOR