Samsung S3C2451X User Manual page 575

S3C2451X RISC MICROPROCESSOR
Video Main Control 1 Register
Register
VIDCON1 0x4C800004
VIDCON1
LINECNT [26:16]
(read only)
Reserved
VSTATUS [14:13]
HSTATUS [12:11]
Reserved [10:8]
IVCLK
IHSYNC
IVSYNC
IVDEN
Reserved [3:0]
VIDEO Time Control 0 Register
Register
VIDTCON0 0x4C800008
VIDTCON0
VBPD [23:16]
VFPD [15:8]
VSPW [7:0]
Address R/W
R/W Video control 2 register
Bit
Provide the status of the line counter (read only)
Up count from 0 to LINEVAL
[15] Reserved
Vertical Status (read only).
00 = VSYNC
10 = ACTIVE
Horizontal Status (read only).
00 = HSYNC
10 = ACTIVE
Reserved
[7] This bit controls the polarity of the VCLK active edge.
0 = The video data is fetched at VCLK falling edge
1 = The video data is fetched at VCLK rising edge
[6] This bit indicates the HSYNC pulse polarity.
0 = normal(active high)
[5] This bit indicates the VSYNC pulse polarity.
0 = normal(active high)
[4] This bit indicates the VDEN signal polarity.
0 = normal(active high)
Reserved
Address R/W
R/W Video time control 1 register
Bit
Vertical back porch is the number of inactive lines at the start of a
frame, after vertical synchronization period. (Period : VBPD +1)
Vertical front porch is the number of inactive lines at the end of a
frame, before vertical synchronization period. (Period : VFPD +1)
Vertical sync pulse width determines the VSYNC pulse's level
width by counting the number of inactive lines.
(Period : VSPW +1)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
01 = BACK Porch
11 = FRONT Porch
01 = BACK Porch
11 = FRONT Porch
1 = inverted(active low)
1 = inverted(active low)
1 = inverted(active low)
Description
Description
LCD CONTROLLER
Reset Value
0x0000_0000
Initial state
0
0
0
0
0
0
0
0
0x0
Reset Value
0x0000_0000
Initial State
0x00
0x00
0x00
22-35