Samsung S3C2451X User Manual page 517

S3C2451X RISC MICROPROCESSOR
NORMAL INTERRUPT STATUS ENABLE REGISTER
Setting to 1 enables Interrupt Status.
Register
NORINTSTSEN0
NORINTSTSEN1
Name Bit
[15]
[14]
ENSTAFIA3
[13]
ENSTAFIA2
[12]
ENSTAFIA1
[11]
ENSTAFIA0
ENSTARWAI
[10]
T
[9]
ENSTACCS
ENSTACAR
[8]
DINT
ENSTACAR
[7]
DREM
ENSTACAR
[6]
DNS
Address R/W
0X4AC00034 R/W
0X4A800034 R/W
Fixed to 0
The Host Driver shall control error interrupts using the Error Interrupt
Status Enable register. (RO)
FIFO SD Address Pointer Interrupt 3 Status Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 2 Status Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 1 Status Enable
'1' = Enabled
'0' = Masked
FIFO SD Address Pointer Interrupt 0 Status Enable
'1' = Enabled
'0' = Masked
Read Wait interrupt status enable
'1' = Enabled
'0' = Masked
CCS Interrupt Status Enable
'1' = Enabled
'0' = Masked
Card Interrupt Status Enable
If this bit is set to 0, the Host Controller shall clear interrupt request
to the System. The Card Interrupt detection is stopped when this bit
is cleared and restarted when this bit is set to 1. The Host Driver
should clear the Card Interrupt Status Enable before servicing the
Card Interrupt and should set this bit again after all interrupt
requests from the card are cleared to prevent inadvertent interrupts.
'1' = Enabled
'0' = Masked
Card Removal Status Enable
'1' = Enabled
'0' = Masked
Card Insertion Status Enable
'1' = Enabled
'0' = Masked
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Normal Interrupt Status Enable Register
(Channel 0)
Normal Interrupt Status Enable Register
(Channel 1)
Description
HSMMC CONTROLLER
Reset Value
0x0
0x0
Initial Value
0
0
0
0
0
0
0
0
0
0
21-49