Samsung S3C2451X User Manual page 505

S3C2451X RISC MICROPROCESSOR
BLOCK GAP CONTROL REGISTER
This register contains the SD Command Argument.
Register
BLKGAP0
BLKGAP1
Name Bit
[7:4]
Reserved
Interrupt At Block Gap
ENINT [3]
This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the
BGAP
interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple
block transfer. Setting to 0 disables interrupt detection during a multiple block transfer.
If the SD card cannot signal an interrupt during a multiple block transfer, this bit
should be set to 0. When the Host Driver detects an SD card insertion, it shall set this
bit according to the CCCR of the SDIO card. (RW)
'1' = Enabled
'0' = Disabled
Read Wait Control
ENRW [2]
The read wait function is optional for SDIO cards. If the card supports read wait, set
AIT
this bit to enable use of the read wait protocol to stop read data using the DAT[2] line.
Otherwise the Host Controller has to stop the SD Clock to hold read data, which
restricts commands generation. When the Host Driver detects an SD card insertion, it
shall set this bit according to the CCCR of the SDIO card. If the card does not support
read wait, this bit shall never be set to 1 otherwise DAT line conflict may occur. If this
bit is set to 0, Suspend/Resume cannot be supported. (RW)
'1' = Enable Read Wait Control
'0' = Disable Read Wait Control
Continue Request
CONT [1]
This bit is used to restart a transaction which was stopped using the Stop At Block
REQ
Gap Request. To cancel stop at the block gap, set Stop At Block Gap Request to 0
and set this bit 1 to restart the transfer.
The Host Controller automatically clears this bit in either of the following cases:
(1) In the case of a read transaction, the DAT Line Active changes from 0 to 1 as a
read transaction restarts.
(2) In the case of a write transaction, the Write Transfer Active changes from 0 to 1
as the write transaction restarts.
Therefore it is not necessary for Host Driver to set this bit to 0. If Stop At Block Gap
Request is set to 1, any write to this bit is ignored. (RWAC)
'1' = Restart
'0' = Not affect
Stop At Block Gap Request
STOP [0]
This bit is used to stop executing a transaction at the next block gap for both DMA and
BGAP
non-DMA transfers. Until the Transfer Complete is set to 1, indicating a transfer
completion the Host Driver shall leave this bit set to 1.
Clearing both the Stop At Block Gap Request and Continue Request shall not
cause the transaction to restart. Read Wait is used to stop the read transaction at the
Address
0X4AC0002A
0X4A80002A
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
R/W
R/W Block Gap Control Register (Channel
0)
R/W Block Gap Control Register (Channel
1)
Description
HSMMC CONTROLLER
Description Reset Value
0x0
0x0
Initial
Value
0
0
0
0
0
21-37