Samsung S3C2451X User Manual page 138

MOBILE DRAM CONTROLLER
Mobile DDR (and DDR2) Memory Interface Examples
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
6-6
Specifications and information herein are subject to change without notice.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A14
A15
DQM0
DQM1
DQS0
DQS1
SCKE
SCLK
SCLKn
Figure 6-2. Memory Interface with 16-bit Mobile DDR and DDR2
DQ0
A0
DQ1
A1
DQ2
A2
DQ3
A3
DQ4
A4
DQ5
A5
DQ6
A6
DQ7
A7
DQ8
A8
DQ9
A9
DQ10
A10
DQ11
A11
DQ12
A12
DQ13
BA0
DQ14
BA1
DQ15
LDQM
UDQM
nSCS
DQS0
nSRAS
DQS1
nSCAS
CKE
nWE
CK
nCK
S3C2451X RISC MICROPROCESSOR
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
nSCS0
nSRASn
SCASn
WE