Samsung S3C2451X User Manual page 141

S3C2451X RISC MICROPROCESSOR
Moble DRAM Configuration Register
Register
BANKCFG
BANKCFG
Reserved [31:19]
RASBW0 [18:17]
Reserved [16]
RASBW1 [15:14]
Reserved [13]
CASBW0 [12:11]
Reserved [10]
CASBW1 [9:8]
ADDRCFG0 [7:6]
ADDRCFG1 [5:4]
MEMCFG [3:1]
BW
Address R/W
0x48000000 R/W
Bit
Reserved
The bit width of RAS (row) address of bank 0
00 = 11-bit
10 = 13-bit
Reserved
The bit width of RAS (row) address of bank 1
00 = 11-bit
10 = 13-bit
Reserved
The bit width of CAS (column) address of bank 0
00 = 8-bit
10 = 10-bit
Reserved
The bit width of CAS (column) address of bank 1
00 = 8-bit
10 = 10-bit
Memory address configuration of
00 = {BA, RAS, CAS}
Memory address configuration
00 = {BA, RAS, CAS}
000 = SDR
011 = 100 = 101 = 111 = Reserved
Determine external memory data bus width
[0]
0 = 32-bit
Description
Mobile DRAM configuration register
Description
01 = {RAS, BA, CAS}
01 = {RAS, BA, CAS}
001 = DDR2 010 = mSDR
1 = 16-bit
MOBILE DRAM CONTROLLER
01 = 12-bit
11 = 14-bit
01 = 12-bit
11 = 14-bit
01 = 9-bit
11 = 11-bit
01 = 9-bit
11 = 11-bit
110 = mDDR
Reset Value
0x0000_000C
Initial State
0x0000
00b
0b
00b
0b
00b
0b
00b
0b
0b
110b
0b
6-9