Samsung S3C2451X User Manual page 391

S3C2451X RISC MICROPROCESSOR
ENDPOINT STATUS REGISTER (ESR)
The endpoint status register reports current status of an endpoint (except EP0) to the MCU
Register Address
ESR 0x4980_002C
ESR Bit
[31:12]
FPID [11]
OSD [10]
DTCZ [9]
SPT [8]
DOM [7]
R/W
R/W Endpoint Status Register
R/W
Reserved
R/W First OUT Packet interrupt Disable in OUT DMA operation.
First Received OUT packet generates interrupt if this bit is
disabled and DEN in DMA control register is enabled
0 = Disable
1 = Enable
R/C OUT Start DMA Operation.
OSD is set when First OUT packet is received after
Registers related DMA Operation are set.
R/C DMA Total Count Zero
DTCZ is set when DMA Operation Total Counter reach to 0.
This bit is cleared when the MCU writes 1 on it.
R/C Short Packet Received.
SPT informs that OUT endpoint receives short packet during
OUT DMA Operation.
This bit is cleared when the MCU writes 1 on it.
R Dual Operation Mode
DOM is set when the max packet size of corresponding
endpoint is equal to a half FIFO size.
This bit is read only.
Endpoint0 does not support dual mode.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
USB2.0 DEVICE
Reset Value
0x0
Initial State
0
0
0
0
0
17-19