Samsung S3C2451X User Manual page 68

SYSTEM CONTROLLER
BLOCK DIAGRAM
Clock
Clocks
Generator
AHB
Figure 2-1 shows the system controller block diagram. The system controller is divided into two blocks, which are
the OFF block and the ON block. Since the system controller must be alive when the external power supply is
disabled. The ALIVE-part is supplied by an auxiliary power source and waits until external/internal interrupts.
However, the OFF-part is disabled when the power-down mode is SLEEP. The clock generator makes all internal
clocks, which include ARMCLK for the ARM core, HCLK for the AHB blocks, PCLK for the APB block, and other
special clocks. The special functional registers (SFR) are located at the register blocks, and their values are
configured through AHB interface. If a software want to change into a power-down mode, then the power
management blocks detect the values within the SFR and change the mode. In addition, they assert the external
power ON/OFF signal if required. All reset signals are generated at the reset control block.
The detailed explanations for each block will be described in the following sections.
Preliminary product information describe products that are in development,
2-2
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
off-part
Glue
Power Management
Register
Figure 2-1. System controller block diagram
S3C2451X RISC MICROPROCESSOR
alive-part
Glue
Signal Power Management
Masking
Register
Reset
Reset
Control
Power
ON/OFF