Samsung S3C2451X User Manual page 470

HSMMC CONTROLLER
BLOCK DIAGRAM
INTREQ
System
Bus
(AHB)
AHB slave I/F
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-2
Specifications and information herein are subject to change without notice.
HCLK
Domain
SFR
Status
CM
D A RG
Control
DM
A
controller
AHB master
Figure 21-1HSMMC block diagram
BaseCLK
Clock Control
Lin
e
Control
FIFO
Control
DPSRA
M
S3C2451X RISC MICROPROCESSOR
SDCLK
Domain
Status
RSP
CMDRS
P packet
Control
Control
Status
DATA
packet
Pad
I/F