Samsung S3C2451X User Manual page 536

HSMMC CONTROLLER
ADMA ERROR STATUS REGISTER
When ADMA Error Interrupt is occurred, the ADMA Error States field in this register holds the ADMA state
and the ADMA System Address Register holds the address around the error descriptor. For recovering the
error, the Host Driver requires the ADMA state to identify the error descriptor address as follows:
ST_STOP: Previous location set in the ADMA System Address register is the error descriptor address
ST_FDS: Current location set in the ADMA System Address register is the error descriptor address
ST_CADR: This sate is never set because do not generate ADMA error in this state.
ST_TFR: Previous location set in the ADMA System Address register is the error descriptor address
In case of write operation, the Host Driver should use ACMD22 to get the number of written block rather
than using this information, since unwritten data may exist in the Host Controller.
The Host Controller generates the ADMA Error Interrupt when it detects invalid descriptor data (Valid=0) at
the ST_FDS state. In this case, ADMA Error State indicates that an error occurs at ST_FDS state. The Host
Driver may find that the Valid bit is not set in the error descriptor.
Register
ADMAERR0
ADMAERR1
Name Bit
[31:11]
[10]
[9]
[8]
[7:3]
[2]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-68
Specifications and information herein are subject to change without notice.
Address
0X4AC00054
0X4A800054
Reserved
ADMA Final Block Transferred (ROC)
In ADMA operation mode, this field is set to High when the Transfer
Complete condition and the block is final (no block transfer remains).
If this bit is Low when the Transfer Complete condition, Transfer
Complete is done due to the Stop at Block Gap, so data to be
transferred still remains.
ADMA Continue Request (WO)
When the stop state by ADMA Interrupt, ADMA operation continues
by setting this bit to HIGH.
ADMA Interrupt Status (RW1C)
This bit is set to HIGH when INT attribute in the ADMA Descriptor
Table is asserted. This bit is not affected by ADMA error interrupt.
Reserved
ADMA Length Mismatch Error
This error occurs in the following 2 cases.
(1) While Block Count Enable being set, the total data length specified
by the Descriptor table is different from that specified by the Block
Count and Block Length.
(2) Total data length can not be divided by the block length.
'0' = No Error
R/W
R/W ADMA Error Status Register (Channel 0)
R/W ADMA Error Status Register (Channel 1)
Description
S3C2451X RISC MICROPROCESSOR
Description Reset Value
0x00
0x00
Initial Value
0x00
0
0
0
0
00