Samsung S3C2451X User Manual page 169

S3C2451X RISC MICROPROCESSOR
7.13.10 NFCON STATUS REGISTER
Register Address
NFSTAT 0x4E000028 R/W NAND Flash operation status register
NFSTAT
Reserved
Reserved
ECCDecDone
IllegalAccess
RnB_TransDetect
NCE[1]
(Read-only)
NCE[0]
(Read-only)
Reserved
RnB
(Read-only)
R/W
Bit
[31:24] Read undefined
[23:7] Reserved
[6] When 4-bit ECC or 8-bit ECC decoding is finished, this value set
and issue interrupt if enabled. The NFMLCBITPT, NFMLCL0 and
NFMLCEL1 have valid values. To clear this, write '1'.
1: 4-bit ECC or 8-bit ECC decoding is completed
[5] Once Soft Lock or Lock-tight is enabled, The illegal access
(program, erase) to the memory makes this bit set.
0: illegal access is not detected
1: illegal access is detected
[4] When RnB low to high transition is occurred, this value set and
issue interrupt if enabled. To clear this write '1'.
0: RnB transition is not detected
1: RnB transition is detected
Transition configuration is set in RnB_TransMode(NFCONT[8]).
[3] The status of nRCS[1] output pin
[2] The status of nFCE output pin
[1] Reserved
[0] The status of RnB input pin.
0: NAND Flash memory busy
1: NAND Flash memory ready to operate
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
NAND FLASH CONTROLLER
Reset Value
0x0080001D
Initial State
0x00
0x00
0
0
1
1
1
0
1
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