Samsung S3C2451X User Manual page 683

S3C2451X RISC MICROPROCESSOR
The Data is aligned in the RX FIFO for 24-bits/channel BLC as shown
31
INVALID
INVALID
INVALID
INVALID
The RXCHPAUSE in the I2SCON register can stop the serial data reception on the I2SSDI.The reception is
stopped once the current Left/Right channel is received
If the control registers in the I2SCON Register (I2S Control Register)and I2SMOD Register (I2S Mode
Register) are to be reprogrammed then it is advisable to disable the RX channel.
The Status of RX FIFO can be checked by checking the bits in the I2SFIC Register (I2S FIFO Control
Register).
23
Figure 26-7: RX FIF0 Structure for BLC = 10 (24-bits/channel)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
BLC = 10 (24-bits/channel)
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
IIS MULTI AUDIO INTERFACE
0
LOC 0
LOC 1
LOC 2
LOC 3
LOC 4
LOC 5
LOC 6
LOC 7
LOC 8
LOC 9
LOC 10
LOC 11
LOC 12
LOC 13
LOC 14
LOC 15
26-13