Samsung S3C2451X User Manual page 491

S3C2451X RISC MICROPROCESSOR
Block Count Enable
ENBLKC [1]
This bit is used to enable the Block Count register, which is only relevant for
NT
multiple block transfers. When this bit is 0, the Block Count register is disabled,
which is useful in executing an infinite transfer. (Refer to the Table
below "Determination of Transfer Type" )
1 = Enable
0 = Disable
ENDMA [0] DMA Enable
This bit enables DMA functionality. DMA can be enabled only if it is supported as
indicated in the DMA Support in the Capabilities register. If DMA is not
supported, this bit is meaningless and shall always read 0. If this bit is set to 1, a
DMA operation shall begin when the Host Driver writes to the upper byte of
Command register (00Fh).
1 = Enable
0 = Disable
Table below shows the summary of how register settings determine types of data transfer.
Multi/Single Block Select
0
1
1
1
Note : For CE-ATA access, (Auto) CMD12 should be issued after Command Completion Signal Disable
Block Count Enable
Don't care
0
1
1
Determination of Transfer Type
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Block Count
Don't care
Don't care
Not Zero
Zero
HSMMC CONTROLLER
0
0
Function
Single Transfer
Infinite Transfer
Multiple Transfer
Stop Multiple Transfer
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