Samsung S3C2451X User Manual page 566

LCD CONTROLLER
VTIME CONTROLLER OPERATION
RGB INTERFACE
The VTIME generates the control signals such as, RGB_VSYNC, RGB_HSYNC, RGB_VDEN and RGB_VCLK
signal for RGB interface. These control signals are highly related with the configuration on the VIDTCON0/1/2
registers in the VSFR register. Base on these programmable configurations of the display control registers in
VSFR, the VTIME module can generate the programmable control signals suitable for the support of many
different types of display device.
The RGB_VSYNC signal is asserted to cause the LCD's line pointer to start over at the top of the display. The
RGB_VSYNC and RGB_HSYNC pulse generation is controlled by the configuration of both the HOZVAL field and
the LINEVAL registers. The HOZVAL and LINEVAL can be determined by the size of the LCD panel according to
the following equations:
HOZVAL = (Horizontal display size) -1
LINEVAL = (Vertical display size) –1
The rate of RGB_VCLK signal can be controlled by the CLKVAL field in the VIDCON0 register. The table below
defines the relationship of RGB_VCLK and CLKVAL. The minimum value of CLKVAL is 1.
RGB_VCLK (Hz) =HCLK/ [CLKVAL+1]
Table 22-5. Relation between VCLK and CLKVAL (Freq. of Video Clock Source=60MHz)
CLKVAL
1
2
:
63
The RGB_HSYNC and RGB_VSYNC signal is configured by RGB_VSYNC, VBPD, VFPD, HSYNC, HBPD,
HFPD, HOZVAL and LINEVAL. Refer the Figure 22-10.
The frame rate is RGB_VSYNC signal frequency. The frame rate is related with the field of RGB_VSYNC, VBPD,
VFPD, LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, CLKVAL registers. Most LCD drivers need their own
adequate frame rate. The frame rate is calculated as follows;
Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1)
+ (HFPD+1) + (HOZVAL + 1) } x { (CLKVAL+1 ) / ( Frequency of Clock source ) } ]
i80-SYSTEM INTERFACE
The VTIME generates the control signals such as, SYS_CS0, SYS_CS1, SYS_RS and SYS_WE signal for i80-
System Interface. The LCDIFMODE, LCD_CS_SETUP, LCD_WAIT_WR and LCD_HOLD_WR registers control
these signals. Refer to figure 22-11.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
22-26
Specifications and information herein are subject to change without notice.
60MHz/X
60 MHz/2
60 MHz/3
:
60 MHz/64
S3C2451X RISC MICROPROCESSOR
VCLK
30.0 MHz
15.0 MHz
:
938 kHz