Samsung S3C2451X User Manual page 176

NAND FLASH CONTROLLER
7.13.16 8BIT ECC MAIN DATA ECC 0/1/2/3 STATUS REGISTER
Register Address
NFM8ECC0 0x4E00_0050
NFM8ECC1 0x4E00_0054
NFM8ECC2 0x4E00_0058
NFM8ECC3 0x4E00_005
C
NFM8ECC0 Bit
th
4 Parity [31:24]
rd
3 Parity [23:16]
nd
2 Parity [15:8]
st
1 Parity [7:0]
NFM8ECC1 Bit
th
8 Parity [31:24]
th
7 Parity [23:16]
th
6 Parity [15:8]
th
5 Parity [7:0]
NFM8ECC2 Bit
th
12 Parity [31:24]
th
11 Parity [23:16]
th
10 Parity [15:8]
th
9 Parity [7:0]
NFM8ECC3 Bit
Reserved [31:8]
th
13 Parity [7:0]
Note: The NAND flash controller generate these ECC parity codes when write main area data while the
MainECCLock (NFCON[7]) bit is '0'(unlock).
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
7-28
Specifications and information herein are subject to change without notice.
R/W
R 8bit ECC status register
R 8bit ECC status register
R 8bit ECC status register
R 8bit ECC status register
th
4 Check Parity generated from main area (512-byte)
rd
3 Check Parity generated from main area (512-byte)
nd
2 Check Parity generated from main area (512-byte)
st
1 Check Parity generated from main area (512-byte)
th
8 Check Parity generated from main area (512-byte)
th
7 Check Parity generated from main area (512-byte)
th
6 Check Parity generated from main area (512-byte)
th
5 Check Parity generated from main area (512-byte)
th
12 Check Parity generated from main area (512-byte)
th
11 Check Parity generated from main area (512-byte)
th
10 Check Parity generated from main area (512-byte)
th
9 Check Parity generated from main area (512-byte)
Reserved
th
13 Check Parity generated from main area (512-byte)
S3C2451X RISC MICROPROCESSOR
Description
Description
Description
Description
Description
Reset Value
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
Initial State
0xXX
0xXX
0xXX
0xXX
Initial State
0xXX
0xXX
0xXX
0xXX
Initial State
0xXX
0xXX
0xXX
0xXX
Initial State
0x000000
0x00