Samsung S3C2451X User Manual page 384

USB2.0 DEVICE
SYSTEM STATUS REGISTER (SSR)
This register reports operational status of the USB 2.0 Function Core, especially about error status and power
saving mode status. Except the line status, every status bits in the System Status Register could be an interrupt
sources. When the register is read after an interrupt due to certain system status changes, MCU should write
back 1 to the corresponding bits to clear it.
Register Address
SSR 0x4980_001C
SSR Bit
[31:16]
BAERR [15]
TMERR [14]
BSERR [13]
TCERR [12]
DCERR [11]
EOERR [10]
[9:8]
TBM [7]
DP [6]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
17-12
Specifications and information herein are subject to change without notice.
R/W
R/C Test Register
R/W
Reserved
R/C Byte Align Error
If error interrupt enable bit of SCR register is set to 1,
BAERR is set to 1 when byte alignment error is detected.
R/C Timeout Error
If error interrupt enable bit of SCR register is set to 1,
TMERR is set to 1 when timeout error is detected.
R/C Bit Stuff Error
If error interrupt enable bit of SCR register is set to 1,
BSERR is set to 1 when bit stuff error is detected.
R/C Token CRC Error
If error interrupt enable bit of SCR register is set to 1,
BSERR is set to 1 when CRC error in token packet is
detected.
R/C Data CRC Error
If error interrupt enable bit of SCR register is set to 1,
DCERR is set to 1 when CRC error in data packet is
detected.
R/C EB OVERRUN Error
If error interrupt enable bit of SCR register is set to 1,
EOERR is set to 1 when EB overrun error in transceiver is
detected.
Reserved
R/C Toggle Bit Mismatch.
If error interrupt enable bit of SCR register is set to 1, TBM
is set to 1 when Toggle mismatch is detected.
R DP Data Line State
DP informs the status of D+ Line
S3C2451X RISC MICROPROCESSOR
Description
Description
Reset Value
0x0
Initial State
0
0
0
0
0
0
0
0