Samsung S3C2451X User Manual page 495

S3C2451X RISC MICROPROCESSOR
32-bit bus system. Parts of the response, the Index field and the CRC, are checked by the Host Controller (as
specified by the Command Index Check Enable and the Command CRC Check Enable bits in the Command
register) and generate an error interrupt if an error is detected. The bit range for the CRC check depends on the
response length. If the response length is 48, the Host Controller shall check R[47:1], and if the response length is
136 the Host Controller shall check R[119:1].
Since the Host Controller may have a multiple block data DAT line transfer executing concurrently with a
CMD_wo_DAT command, the Host Controller stores the Auto CMD12 response in the upper bits (REP[127:96]) of
the Response register. The CMD_wo_DAT response is stored in REP[31:0]. This allows the Host Controller to
avoid overwriting the Auto CMD12 response with the CMD_wo_DAT and vice versa.
When the Host Controller modifies part of the Response register, as shown in the Table above, it shall preserve
the unmodified bits.
Note : CMD_wo_DAT (Command without Data line) means the command not to use data line. The
command set of this type depends on the card type (MMC, SD/SDIO or CE-ATA). Generally, the
command using data line receives contents through "Buffer Data Port Register", but the command
without using data line receives contents through "RESPONSE register" in the Host Controller.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
HSMMC CONTROLLER
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