Samsung S3C2451X User Manual page 652

IIS-BUS INTERFACE
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTIONS
IIS interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel
control block as shown in Figure 25-1. Note that each FIFO has 32-bit width and 16 depth structure, which
contains left/right channel data. So, FIFO access and data transfer are handled with left/right pair unit. Figure 25-1
shows the internal functional block diagram of IIS interface, for actual GPIO pad name, please refer prior page's
SIGNALS table. For more detail guide of GPIO setting, please refer the GPIO chapter.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
25-2
Specifications and information herein are subject to change without notice.
Figure 25-1. IIS-Bus Block Diagram
S3C2451X RISC MICROPROCESSOR