Samsung S3C2451X User Manual page 72

SYSTEM CONTROLLER
CLOCK MANAGEMENT
CLOCK GENERATION OVERVIEW
Figure 2-3 shows the block diagram of the clock generation module. The main clock source comes from an
external crystal (XTI) or external clock (EXTCLK). EPLL's input clock is one of the XTI or EXTCLK. Clock selection
can be done by configuring MUX selection signal. When both XTI and EXTCLK are running, GFM(Glitch Free
Mux)'s output can be configured easily without generating glitch. But If you change or select EPLL input clock
when either XTI or EXTCLK is running, disabled clock should be have logic LOW.
XTI clock source can be reference of PLL after oscillated at PAD. User can configure stabilization time by setting
OSCSET register and ON/OFF when power-down mode by setting PWRCFG register.The clock generator
consists of two PLLs (Phase-Locked-Loop) which generate the high-frequency clock signals required in
S3C2451X.
XTI
EXTCLK
XTI
EXTCLK
CLOCK SOURCE SELECTION
Table 2-2 and 2-3 show the relationship between the combination of mode control pins OM[0] and the selection of
source clock for S3C2451X.
Table 2-2. Clock source selection for the main PLL and clock generation logic
Preliminary product information describe products that are in development,
2-6
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
OM[0]
MPLL
ExtClk Div
EPLL
OM[0]&
CLKSRC
Figure 2-3. Clock generator block diagram
OM[0]
0
1
S3C2451X RISC MICROPROCESSOR
SYSCLK
Clock
Divider &
Mux
ECLK
MPLL Reference Clock
(Main clock source)
XTI
EXTCLK
ARMCLK
HCLK
PCLK
DDRCLK
USBHOST
CAMCLK
LCDCLK
I2SCLK
UARTCLK