Samsung S3C2451X User Manual page 133

Risc microprocessor
Table of Contents

Advertisement

S3C2451X RISC MICROPROCESSOR
6
MOBILE DRAM CONTROLLER
OVERVIEW
The S3C2451 Mobile DRAM Controller supports three kinds of memory interface - (Mobile) SDRAM and mobile
DDR and DDR2. Mobile DRAM controller provides 2 chip select signals (2 memory banks), these are used for up
to 2 (mobile) SDRAM banks or 2 mobile DDR banks or 2 DDR2 banks. Mobile DRAM controller can't support 3
kinds of memory interface simultaneous, for example one bank for (mobile) SDRAM and one bank for mobile
DDR.
Mobile DRAM controller has the following features:
Support little endian
Mobile DDR SDRAM and (Mobile) SDRAM
Supports 32-bit for SDRAM and 16-bit data bus interface for mDDR and DDR2.
Address space: up to 128Mbyte
Supports 2 banks: 2-nCS (chip selection)
16-bit Refresh Timer
Self Refresh Mode support (controlled by power management)
Programmable CAS Latency
Provide Write buffer: 8-word size
Provide pre-charge and active power down mode
Provide power save mode
Support extended MRS for mobile DRAM)
DS, TSCR, PASR
DDR2 Features
Support DDR2 having 4-bank architecture, don't support 8-bank architecture.
Support 16-bit external data bus interface
Support AL(Additive Latency) 0, don't support posted CAS, it needs EMRS setting.
Don't support ODT and nDQS function, it needs EMRS setting.
All other features are same to the features of SDR/mDDR
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MOBILE DRAM CONTROLLER
6-1

Advertisement

Chapters

Table of Contents
loading

Table of Contents