Samsung S3C2451X User Manual page 38

PRODUCT OVERVIEW
S3C2451X OPERATION MODE DESCRIPTION
OM[4] OM[3] OM[2]
0
0
1
1 0
* OM[0] selects the clock source of MPLL/EPLL
( You can select different EPLL clock source with that of MPLL by software setting – refer to SYSCON)
* addr(x) means the number of address cycle during NAND Flash operation.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
1-34
Specifications and information herein are subject to change without notice.
Table 1-5. S3C2451X Operation Mode Description
OM[1] OM[0]
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
OM[4] OM[3] OM[2]
page(4K)
N
A Large
N Block
D
page(2K)
iROM
Reserved
N
A Small
page(512)
N Block
D
Reserved
JTAG
OneNAND
(Muxed)
OneNAND/
ROM/
ROM
OneNAND
(Demuxed)
S3C2451X RISC MICROPROCESSOR
OM[1] OM[0]
OSC
addr(4)
EXT
OSC
addr(5)
EXT
OSC
addr(4)
EXT
OSC
addr(5)
EXT
OSC
EXT
OSC
addr(3)
EXT
OSC
addr(4)
EXT
OSC
16-bit
EXT
OSC
8-bit
EXT
OSC
16-bit
EXT
Operation
Mode
NAND
iROM
Reserved
NAND
Reserved
JTAG
OneNAND
(Muxed)
ROM/
OneNAND
(Demuxed)