Samsung S3C2451X User Manual page 749

S3C2451X RISC MICROPROCESSOR
(VDDi= 1.3V± 0.05V (400MHz), VDDi= TBD V± 0.05V (533MHz), TA = -40 to 85°C, VDD_OP2 = 3.3V ± 0.3V)
Parameter
eXternal Request Setup
aCcess to Ack Delay when Low transition
aCcess to Ack Delay when High transition
eXternal Request Delay
Table 29-17. TFT LCD Controller Module Signal Timing Constants
(VDDi= 1.3V± 0.05V (400MHz), VDDi= TBD V± 0.05V (533MHz), TA = -40 to 85°C, VDD_LCD = 3.3V ± 0.3V)
Parameter
VCLK pulse width
VCLK pulse width high
VCLK pulse width low
Vertical sync pulse width
Vertical back porch delay
Vertical front porch dealy
Hsync setup to VCLK falling edge
VDEN set up to VCLK falling edge
VDEN hold from VCLK falling edge
VD setup to VCLK falling edge
VD hold from VCLK falling edge
VSYNC setup to HSYNC falling edge
VSYNC hold from HSYNC falling edge
NOTES :
1. VCLK period
2. HSYNC period
Table 29-18. IIS Controller Module Signal Timing Constants(I2S Master Mode Only)
(VDDi= 1.3V± 0.05V (400MHz), VDDi= TBD V± 0.05V (533MHz), TA = –40 to 85 °C, VDD_OP2 = 3.3V ± 0.3V)
Parameter
LR Clock Input Delay
Serial Data Setup Time
Serial Data Hold Time
Table 29-16. DMA Controller Module Signal Timing Constants
Tde2csetup
Tde2chold
Tvd2csetup
Tvd2chold
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Symbol
t
XRS
t
CADL
t
CADH
t
XAD
Symbol Min
Tvclk 18
Tvclkh 0.3
Tvclkl 0.3
Tvspw VSPW + 1
Tvbpd VBPD+1
Tvfpd VFPD+1
Tl2csetup 0.3
0.3
0.3
0.3
0.3
Tf2hsetup HSPW + 1
Tf2hhold HBPD + HFPD +
HOZVAL + 3
Symbol Min.
TLRId 5
TDS 10
TDH 10
Min Typ
6.4/6.4 –
3.1/2.8
2.8/2.5
2 –
Typ
200
–
–
–
–
–
–
–
–
–
–
–
–
Typ. Max
-
-
-
ELECTRICAL DATA
Max Unit
9.9/9.9 ns
7.8/7.1 ns
7.8/6.9 ns
– HCLK
Max Units
– ns
– Pvclk(1)
– Pvclk
– Phclk(2)
– Phclk
– Phclk
– Pvclk
– Pvclk
– Pvclk
– Pvclk
– Pvclk
– Pvclk
– Pvclk
Unit
13 ns
ns
ns
29-25