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Samsung S3F80JB User Manual

Samsung S3F80JB User Manual

8-bit cmos microcontrollers
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S3F80JB
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1.1

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Summary of Contents for Samsung S3F80JB

  • Page 1 S3F80JB 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.1...
  • Page 2 Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.
  • Page 3 Chapter 14 Comparator Two order forms are included at the back of this manual to facilitate customer order for S3F80JB microcontrollers: the Flash Factor Writing Order Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.

  • Page 4: Table Of Contents

    Part I — Programming Model Chapter 1 Product Overview S3C8/S3F8-Series Microcontrollers ... 1-1 S3F80JB Microcontroller ... 1-1 Features ... 1-2 Block Diagram (32-pin package) ... 1-3 Block Diagram (44-pin package) ... 1-4 Pin Assignments... 1-5 Pin Circuits ... 1-10 Chapter 2 Address Spaces Overview ...
  • Page 5 Overview ...6-1 Flags Register (FLAGS)...6-6 Flag Descriptions ...6-7 Instruction Set Notation...6-8 Condition Codes...6-12 Instruction Descriptions ...6-13 Chapter 7 Clock Circuit Overview ...7-1 System Clock Circuit ...7-1 Clock Status During Power-Down Modes ...7-2 System Clock Control Register (CLKCON) ...7-3 (Continued) S3F80JB MICROCONTROLLER...
  • Page 6 Hardware Reset Values ... 8-15 Recommendation for Unusued Pins ... 8-19 Summary Table of Back-Up Mode, Stop Mode, and Reset Status... 8-20 Chapter 9 I/O Ports Overview ... 9-1 Port Data Registers... 9-4 Pull-Up Resistor Enable Registers ... 9-5 S3F80JB MICROCONTROLLER (Continued)
  • Page 7 Counter A Pulse Width Calculations...12-4 Chapter 13 Timer 2 Overview ...13-1 Timer 2 Overflow Interrupt...13-2 Timer 2 Capture Interrupt ...13-2 Timer 2 Match Interrupt ...13-3 Timer 2 Control Register (T2CON)...13-5 Chapter 14 Comparator Overview ...14-1 Comparator Operation ...14-3 viii (Continued) S3F80JB MICROCONTROLLER...
  • Page 8 Chapter 18 Electrical Data – 8MHz Overview ... 18-1 Chapter 19 Mechanical Data Overview······················································································································································ 19-1 Chapter 20 Development Tools Data Overview······················································································································································ 20-1 Target Boards... 20-1 Programming Socket Adapter... 20-1 TB80JB Target Board... 20-2 OTP/MTP Programmer (Writer)... 20-7 S3F80JB MICROCONTROLLER (Continued)
  • Page 9 Indexed Addressing to Program or Data Memory ...3-9 3-10 Direct Addressing for Load Instructions ...3-10 3-11 Direct Addressing for Call and Jump Instructions ...3-11 3-12 Indirect Addressing...3-12 3-13 Relative Addressing...3-13 3-14 Immediate Addressing ...3-14 Register Description Format ...4-4 List of Figures Title Page Number S3F80JB MICROCONTROLLER...
  • Page 10 RESET Sources of The S3F80JB... 8-2 RESET Block Diagram of The S3F80JB ... 8-3 RESET Block Diagram by LVD for The S3F80JB IN STOP MODE ... 8-4 Internal Power-On Reset Circuit ... 8-5 Timing Diagram for Internal Power-On Reset Circuit... 8-6 Reset Timing Diagram for The S3F80JB in STOP mode by IPOR ...
  • Page 11 Timer 2 Block Diagram ...13-4 13-4 Timer 2 Control Register (T2CON) ...13-5 13-5 Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL)...13-6 14-1 Comparator Block Diagram for The S3F80JB...14-2 14-2 Conversion Characteristics...14-3 14-3 Comparator Mode Register (CMOD) ...14-4 14-4 Comparator Input Selection Register (CMPSEL) ...14-4 14-5 Comparator Result Register (CMPREG) ...14-5...
  • Page 12 Input Timing for External Interrupts (Port 0 and Port 2) ············································ 18-10 18-11 Input Timing for Reset (nRESET Pin)······································································· 18-10 18-12 Operating Voltage Range of S3F80JB ····································································· 18-13 19-1 32-Pin SOP Package Dimension... 19-1 19-2 44-Pin QFP Package Dimension ... 19-2 20-1 TB80JB Target Board Configuration·········································································...
  • Page 13 Reset Generation According to the Condition of Smart Option... 8-18 Guideline for Unused Pins to Reduced Power Consumption... 8-19 Summary of Each Mode ... 8-20 S3F80JB Port Configuration Overview (44-QFP) ... 9-2 S3F80JB Port Configuration Overview (32-SOP) ... 9-3 Port Data Register Summary... 9-4...
  • Page 14 18-9 Oscillation Stabilization Time····················································································18-12 18-10 AC Electrical Characteristics for Internal Flash ROM··············································18-13 20-1 Components Consisting of S3F80JB Target Board ··················································20-3 20-2 Default Setting of the Jumper in S3F80JB Target Board ··········································20-4 List of Tables (Continued) Title Page Number S3F80JB MICROCONTROLLER...
  • Page 15 To Generate 38 kHz, 1/3duty Signal Through P3.1 ... 12-6 To Generate a one Pulse Signal Through P3.1 ... 12-7 Chapter 15 Embedded Flash Memory Interface Sector Erase ... 15-10 Programming... 15-15 Reading... 15-17 Hard Lock Protection ... 15-18 S3F80JB MICROCONTROLLER List of Programming Tips Page Number xvii...
  • Page 16 Register Pointer 1... 4-38 Stack Pointer (Low Byte) ... 4-39 STOPCON Stop Control Register ... 4-39 System Mode Register ... 4-40 T1CON Timer 1 Control Register ... 4-42 T2CON Timer 2 Control Register ... 4-43 S3F80JB MICROCONTROLLER Full Register Name Page Number...
  • Page 17 LDCD/LDED Load Memory and Decrement ... 6-54 LDCI/LDEI Load Memory and Increment... 6-55 LDCPD/LDEPD Load Memory with Pre-Decrement ... 6-56 LDCPI/LDEPI Load Memory with Pre-Increment... 6-57 Load Word... 6-58 MULT Multiply (Unsigned)... 6-59 S3F80JB MICROCONTROLLER Full Register Name Page Number...
  • Page 18 Shift Right Arithmetic ...6-79 SRP/SRP0/SRP1 Set Register Pointer ...6-80 STOP Stop Operation ...6-81 Subtract ...6-82 SWAP Swap Nibbles...6-83 Test Complement Under Mask ...6-84 Test Under Mask ...6-85 Wait For Interrupt...6-86 Logical Exclusive OR...6-87 xxii Full Register Name (Continued) Page Number S3F80JB MICROCONTROLLER...

  • Page 19: Chapter 1 Product Overview

    Fast interrupt processing (within a minimum four CPU clocks) can be assigned to specific interrupt levels. S3F80JB MICROCONTROLLER The S3F80JB single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung's newest CPU architecture. The S3F80JB is the microcontroller which has 64-Kbyte Flash Memory ROM.

  • Page 20: Features

    When V is lower than V Back-up mode to block oscillation and reduce the current consumption. In S3F80JB, this function is disabled when operating state is “STOP mode”. • When reset pin is lower than Input Low Voltage ), the chip enters Back-up mode to block oscillation and reduce the current consumption.

  • Page 21: Block Diagram (32-Pin Package)

    S3F80JB BLOCK DIAGRAM (32-PIN PACKAGE) P0.0-0.3 (INT0-INT3) IPOR(note) Main 8-Bit Basic Timer 8-Bit Timer0 /Counter 16-Bit Timer1 /Counter 16-Bit Timer2 /Counter IPOR can be enabled or disabled by IPOR / LVD control bit in the smart option. (Refer to Figure 2-2) P0.4-P0.7(INT4)

  • Page 22: Block Diagram (44-Pin Package)

    Port1 I/O Port and Interrupt Control SAM8RC CPU 64K-byte 272-byte FLASH Register File Memory Carrier Generator Comparator (Counter A) Figure 1-2. Block Diagram (44-pin) NOTE S3F80JB TEST nRESET P2.0-2.3 (INT5-INT8) Port2 P2.4-2.7 (INT9) (CIN0-CIN3) P3.0/T0PWM/T0CAP/SDAT P3.1/REM/SCLK Port3 P3.2/T0CK P3.3/T1CAP/T2CAP P3.4-P3.5 P4.0-P4.7...

  • Page 23: Pin Assignments

    S3F80JB PIN ASSIGNMENTS XOUT TEST P2.5/INT9/CIN1 P2.6/INT9/CIN2 nRESET P2.7/INT9/CIN3 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Figure 1-3. Pin Assignment Diagram (32-Pin SOP Package) S3F80JB (Top View) 32-SOP PRODUCT OVERVIEW P3.1/REM/T0CK/SCLK P3.0/T0PWM/T0CAP/T1CAP/T2CAP/SDAT P2.4/INT9/CIN0 P2.3/INT8 P2.2/INT7 P2.1/INT6 P2.0/INT5 P0.7/INT4 P0.6/INT4 P0.5/INT4...

  • Page 24: Pin Assignment Diagram (44-Pin Qfp Package)

    PRODUCT OVERVIEW PIN ASSIGNMENTS (Continued) P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4 P4.3 P4.2 P4.1 P4.0 P2.0/INT5 P2.1/INT6 P2.2/INT7 Figure 1-4. Pin Assignment Diagram (44-Pin QFP Package) S3F80JB (Top View) (44-QFP) S3F80JB P1.3 P1.2 P1.1 P4.7 P3.3/T1CAP/T2CAP P3.2/T0CK P1.0 P2.7/INT9/CIN3 P3.5 P3.4 nRESET...

  • Page 25: Pin Descriptions Of 32-Sop

    S3F80JB Names Type I/O port with bit-programmable pins. Configurable P0.0–P0.7 to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED&R (note) circuit built in P0 for STOP releasing.

  • Page 26: Pin Descriptions Of 44-Qfp

    Refer to page 8-11. Table 1-2. Pin Descriptions of 44-QFP Pin Description Circuit 44 Pin Shared Type Functions 30–37 Ext. INT (INT0–INT3) (INT4) – 20–26 42–44 Ext. INT 1, 2, (INT5–INT8) 10,11, (INT9) (CIN0-CIN3) T0PWM/T0CAP (SDAT) S3F80JB...
  • Page 27 S3F80JB Table 1-2. Pin Descriptions of 44-QFP (Continued) Names Type P3.1 I/O port with bit-programmable pin. Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with a pull-up resistor can be assigned by software. This port 3pin has high current drive capability.

  • Page 28: Pin Circuits

    PIN CIRCUITS Pull-up Enable Data Output Disable P2.4-P2.7 Only External Interrupt Stop Figure 1-5. Pin Circuit Type 1 (Port 0 and Port2) 1-10 P2CONx.x CMPSEL.0-.3 External REF (P2.7 only) Comparator Noise Filter Pull-Up Resistor (55kΩ- typ) INPUT/OUTPUT Stop Release S3F80JB...

  • Page 29: Pin Circuit Type 2 (Port 1, Port4, P3.4 And P3.5)

    S3F80JB PIN CIRCUITS (Continued) Pull-up Enable Data Open-Drain Output Disable Normal Input Figure 1-6. Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3.5) Pull-up Resistor (55kΩ-Typ) INPUT/OUTPUT Noise Filter PRODUCT OVERVIEW 1-11...

  • Page 30: Pin Circuit Type 3 (P3.0)

    PRODUCT OVERVIEW PIN CIRCUITS (Continued) Pull-up Enable Port 3.0 Data T0_PWM Open-Drain Output Disable P3.0 Input T0CAP/(T1CAP/T2CAP) 1-12 P3CON.2 Data P3CON.2,6,7 Noise filter Figure 1-7. Pin Circuit Type 3 (P3.0) Pull-up Resistor (55kΩ-Typ) P3.0/T0PWM T0CAP/ (T1CAP/T2CAP) S3F80JB...

  • Page 31: Pin Circuit Type 4 (P3.1)

    S3F80JB PIN CIRCUITS (Continued) Pull-up Enable Port 3.1 Data Carrier On/Off (P3.7) CACON.2 Open-Drain Output Disable P3.1 Input Input T0CK : P3.2 T1CAP/T2CAP: P3.3 P3CON.5 Data P3CON.5,6,7 T0CK Noise filter Figure 1-8. Pin Circuit Type 4 (P3.1) P3CON.2,6,7 Figure 1-9. Pin Circuit Type 5 (P3.2 and P3.3)

  • Page 32: Pin Circuit Type 6 (Nreset)

    PRODUCT OVERVIEW PIN CIRCUITS (Continued) 1-14 Figure 1-10. Pin Circuit Type 6 (nRESET) Pull-up Resistor (500kΩ-Typ) nRESET S3F80JB...

  • Page 33: Overview

    A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3F80JB has a programmable internal 64-Kbytes Flash ROM. An external memory interface is not implemented.

  • Page 34: Chapter 2 Address Spaces

    S3F80JB PROGRAM MEMORY Program memory (Flash memory) stores program code or table data. The S3F80JB has 64-Kbyte of internal programmable Flash memory. The program memory address range is therefore 0000H–FFFFH of Flash memory (See Figure 2-1). The first 256 bytes of the program memory (0H–0FFH) are reserved for interrupt vector addresses. Unused locations (0000H –...

  • Page 35: Smart Option

    Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80JB only use 003EH and 003FH. User can write any value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory is 0FFH (IPOR disable, LVD enable in the stop mode, Normal reset vector address 100H, ISP protection disable).
  • Page 36 S3F80JB 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless. 2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H).

  • Page 37: Register Architecture

    32-byte area is a single 32-byte common area. In case of S3F80JB the total number of addressable 8-bit registers is 333. Of these 333 registers, 22 bytes are for CPU and system control registers, 39 bytes are for peripheral control and data registers, 16 bytes are used as shared working registers, and 272 registers are for general-purpose use.

  • Page 38: Internal Register File Organization

    S3F80JB Control Register (Register Addressing Bytes System Register (Register Addressing Working Register (Working Register Addressing only) Set 1 Bank1 Bank 0 System and Bytes Peripheral Mode) Mode) Bytes Bytes Figure 2-3. Internal Register File Organization ADDRESS SPACES Set 2 Page 0...

  • Page 39: Register Page Pointer (Pp)

    (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer PP (DFH, Set 1, Bank0). In the S3F80JB microcontroller, a paged register file expansion is not implemented and the register page pointer settings therefore always point to “page 0”.

  • Page 40: Register Set1

    The upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two 32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to address one bank or the other. In the S3F80JB microcontroller, bank 1 is implemented.

  • Page 41: Prime Register Space

    S3F80JB PRIME REGISTER SPACE The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) are called the prime register space or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.).

  • Page 42: Working Registers

    S3F80JB WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as consisting of 32 8-byte register groups or "slices." Each slice consists of eight 8-bit registers.

  • Page 43: Using The Register Pointers

    S3F80JB USING THE REGISTER POINTERS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.

  • Page 44: Non-Contiguous 16-Byte Working Register Block

    S3F80JB 1 1 1 1 0 X X X 0 0 0 0 0 X X X Figure 2-8. Non-Contiguous 16-Byte Working Register Block PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H–85H using the register pointer. The register addresses 80H through 85H...

  • Page 45: Register Addressing

    S3F80JB ADDRESS SPACES REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access all locations in the register file except for set 2.

  • Page 46: Register File Addressing

    2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area). NOTE: In the S3F80JB microcontroller,only page0 is implemented.Page0 containsall of the addressable registers in the internal register file. 2-14...

  • Page 47: Common Working Register Area (C0H-Cfh)

    S3F80JB COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file.

  • Page 48: 4-Bit Working Register Addressing

    S3F80JB PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Example 1: 0C2H,40H Use working register addressing instead:...

  • Page 49: Bit Working Register Addressing Example

    S3F80JB Register pointer provides five high-order bits Figure 2-12. 4-Bit Working Register Addressing 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 Figure 2-13. 4-Bit Working Register Addressing Example Selects RP0 or RP1...

  • Page 50: 8-Bit Working Register Addressing

    S3F80JB 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value 1100B.

  • Page 51: Bit Working Register Addressing Example

    S3F80JB 0 1 1 1 0 Specifies working register addressing Figure 2-15. 8-Bit Working Register Addressing Example 0 0 0 Selects RP1 8-bit address from instruction 'LD R11, R2' Register address (0ABH) ADDRESS SPACES 0 0 0 1 0 1...

  • Page 52: System And User Stacks

    Register location D9H contains the 8-bit stack pointer (SPL) that is used for system stack operations. After a reset, the SPL value is undetermined. Because only internal memory 256-byte is implemented in The S3F80JB, the SPL must be initialized to an 8-bit value in the range 00–FFH.

  • Page 53: Standard Stack Operations Using Push And Pop

    S3F80JB PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: SPL,#0FFH • • • PUSH PUSH PUSH PUSH •...

  • Page 54: Chapter 3 Addressing Modes

    S3F80JB ADDRESSING MODES ADDRESSING MODES OVERVIEW The program counter is used to fetch instructions that are stored in program memory for execution. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.

  • Page 55: Register Addressing Mode (R)

    (1 of 8) R1, R2 Where R1 and R2 are registers in the curruntly selected working register area. Figure 3-2. Working Register Addressing Register File OPERAND Register File RP0 or RP1 Selected RP points to start of working register block OPERAND S3F80JB...

  • Page 56: Indirect Register Addressing Mode (Ir)

    S3F80JB INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).

  • Page 57: Indirect Register Addressing To Program Memory

    Instruction References OPCODE Program Memory Sample Instructions: CALL @RR2 @RR2 Figure 3-4. Indirect Register Addressing to Program Memory Points to Register Pair Value used in instruction Register File Register Pair 16-Bit Address Points to Program Program Memory Memory OPERAND S3F80JB...

  • Page 58: Indirect Working Register Addressing To Register File

    S3F80JB INDIRECT REGISTER ADDRESSING MODE (Continued) Program Memory 4-bit Working Register OPCODE Address Sample Instruction: R3, @R6 Figure 3-5. Indirect Working Register Addressing to Register File Register File MSB Points to RP0 or RP1 RP0 or RP1 3 LSBs Point to the...

  • Page 59: Indirect Working Register Addressing To Program Or Data Memory

    Data Memory Sample Instructions: NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB. Figure 3-6. Indirect Working Register Addressing to Program or Data Memory MSB Points to RP0 or RP1 Next 2-bit Point...

  • Page 60: Indexed Addressing Mode (X)

    S3F80JB INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3–7). You can use Indexed addressing mode to access locations in the internal register file or in external memory (if implemented). You cannot, however, access locations C0H–FFH in set 1 using indexed addressing.

  • Page 61: Indexed Addressing To Program Or Data Memory With Short Offset

    Sample Instructions: R4, #04H[RR2] R4,#04H[RR2] NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB. Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset MSB Points to RP0 or RP1 OFFSET...

  • Page 62: Indexed Addressing To Program Or Data Memory

    OPCODE Sample Instructions: R4, #1000H[RR2] R4,#1000H[RR2] NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB. Figure 3-9. Indexed Addressing to Program or Data Memory MSB Points to RP0 or RP1 OFFSET OFFSET NEXT 2 BITS...

  • Page 63: Direct Address Mode (Da)

    Load operations to program memory (LDC) or to external data memory (LDE), if implemented. Sample Instructions: R5,1234H R5,1234H NOTE: LDE command is not available, because an external interface is not implemented for the S3F80JB. Figure 3-10. Direct Addressing for Load Instructions 3-10 Program or Data Memory Memory...

  • Page 64: Direct Addressing For Call And Jump Instructions

    S3F80JB DIRECT ADDRESS MODE (Continued) Sample Instructions: C,JOB1 CALL DISPLAY Figure 3-11. Direct Addressing for Call and Jump Instructions Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Where JOB1 is a 16-bit immediate address...

  • Page 65: Indirect Address Mode (Ia)

    Program Memory Next Instruction LSB Must be Zero OPCODE Lower Address Byte Upper Address Byte ; The 16-bit value in program memory addresses 40H and 41H is the subroutine start address. Figure 3-12. Indirect Addressing S3F80JB Program Memory Locations 0-255...

  • Page 66: Relative Address Mode (Ra)

    S3F80JB RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed.

  • Page 67: Immediate Mode (Im)

    The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers. 3-14 Program Memory OPERAND OPCODE (The operand value is in the instruction) Sample Instruction: R0,#0AAH Figure 3-14. Immediate Addressing S3F80JB...

  • Page 68: Chapter 4 Control Registers

    CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3F80JB control registers are presented in an easy-to-read format. You can use this section as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format.

  • Page 69: Mapped Registers (Bank0, Set1)

    Port 0 Interrupt Pending Register Table 4-1. Mapped Registers (Bank0, Set1) Mnemonic T0CNT T0DATA T0CON BTCON CLKCON FLAGS Location D8H is not mapped. P2INT P2PND P0PUR P0CONH P0CONL P1CONH P1CONL P2CONH P2CONL P2PUR P3CON P4CON P0INT P0PND Decimal S3F80JB (NOTE) (NOTE)

  • Page 70: Mapped Registers (Bank1, Set1)

    S3F80JB Register Name Counter A Control Register Counter A Data Register (High Byte) Counter A Data Register (Low Byte) Timer 1 Counter Register (High Byte) Timer 1 Counter Register (Low Byte) Timer 1 Data Register (High Byte) Timer 1 Data Register (Low Byte)

  • Page 71: Register Description Format

    (Set ) Register address Register address (Hexadecimal) (Bank ) Set1 Bank0 RESET value notation: '-' = Not used 'x' = Undetermind value '0' = Logic zero '1' = Logic one Bit number: MSB = Bit 7 LSB = Bit 0 S3F80JB...

  • Page 72: Btcon Basic Timer Control Register

    BTCON.0 value is automatically cleared to "0". Disable watchdog timer function Enable watchdog timer function /4096 /1024 /128 Not used for S3F80JB. No effect Clear the basic timer counter value No effect Clear both block frequency dividers CONTROL REGISTERS...

  • Page 73: Cacon Counter A Control Register

    Counter A Output Flip-Flop Control Bit Elapsed time for Low data value Elapsed time for High data value Elapsed time for combined Low and High data values Not used for S3F80JB. Disable interrupt Enable interrupt Stop counter A Start counter A...

  • Page 74: Clkcon System Clock Control Register

    CLKCON.3 and CLKCON.4. These selection bits CLKCON.0, .1, .2 are required only for systems that have a main clock and a subsystem clock. The S3F80JB uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid. (non-divided) Not used for S3F80JB.

  • Page 75: Cmod Comparator Mode Register

    Addressing Mode Comparator Enable Bit Conversion Timer Control Bit External Reference Selection Bit Not used for S3F80JB. .3 – .0 Reference Voltage Selection Bits Selected V NOTE: You can select the number of analog input pin for your purpose by setting the CMPSEL.

  • Page 76: Cmpsel Comparator Input Selection Register

    Read/Write – Register addressing mode only Addressing Mode .7– .4 Not used for S3F80JB. P2.7 Function Selection Bit P2.6 Function Selection Bit P2.5 Function Selection Bit P2.4 Function Selection Bit NOTE: If a bit of CMPSEL is set to “1”(Comparator input is selected), the port pin is operated as comparator input regardless of the P2CONH settings.

  • Page 77: Emt External Memory Timing Register

    Not used for S3F80JB NOTE: The EMT register is not used for S3F80JB, because an external peripheral interface is not implemented in the S3F80JB. The program initialization routine should clear the EMT register to '00H' following a reset. Modification of EMT values during normal operation may cause a system malfunction.

  • Page 78: Flags System Flags Register

    S3F80JB FLAGS — System Flags Register Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode Carry Flag Bit (C) Zero Flag Bit (Z) Sign Flag Bit (S) Overflow Flag Bit (V) Decimal Adjust Flag Bit (D) Half-Carry Flag Bit (H)

  • Page 79: Fmcon Flash Memory Control Register

    1010 0110 Others .3 – .1 Not used for S3F80JB Flash Operation Start Bit (available for Erase and Hard Lock mode only) NOTE: Hard Lock mode is one of the flash protection modes. Refer to page 15-18. 4-12 Programming mode...

  • Page 80: Fmsech Flash Memory Sector Address Register (High Byte)

    S3F80JB FMSECH — Flash Memory Sector Address Register(High Byte) ECH Set1 Bank1 Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode .7 – .0 Flash Memory Sector Address (High Byte) Note: The high-byte flash memory sector address pointer value is the higher eight bits of the 16-bit pointer address.

  • Page 81: Imr Interrupt Mask Register

    Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow 4-14 Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) Disable (mask) Enable (un-mask) S3F80JB DDH Set1 Bank0...

  • Page 82: Iph Instruction Pointer (High Byte)

    S3F80JB — Instruction Pointer (High Byte) Bit Identifier Reset Value Read/Write Addressing Mode Register addressing mode only .7 – .1 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL register (DBH).

  • Page 83: Ipr Interrupt Priority Register

    Interrupt Group C Priority Control Bit Interrupt Subgroup B Priority Control Bit Interrupt Group B Priority Control Bit Interrupt Group A Priority Control Bit NOTE: The S3F80JB interrupt structure uses eight levels: IRQ0-IRQ7. 4-16 Group priority undefined B > C > A A >...
  • Page 84 S3F80JB — Interrupt Request Register Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4 Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0 Level 5 (IRQ5) Request Pending Bit; External Interrupts P2.7–P2.4 Level 4 (IRQ4) Request Pending Bit;...

  • Page 85: Lvd Flag

    Register addressing mode only Addressing Mode .7 – .1 Not used for S3F80JB. LVD Flag (2.3V) Indicator Bit NOTE: When LVD detects LVD_FLAG level (2.3V), LVDCON.0 flag bit is set automatically. When VDD is upper 2.3V, LVDCON.0 flag bit is cleared automatically.
  • Page 86 S3F80JB P0CONH — Port 0 Control Register (High Byte) Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode .7 and .6 P0.7/INT4 Mode Selection Bits .5 and .4 P0.6/INT4 Mode Selection Bits .3 and .2 P0.5/INT4 Mode Selection Bits .1 and .0...

  • Page 87: P0Conl Port 0 Control Register (Low Byte)

    C-MOS input mode; interrupt on rising and falling edges Push-pull output mode C-MOS input mode; interrupt on rising edges C-MOS input mode; interrupt on falling edges C-MOS input mode; interrupt on rising and falling edges Push-pull output mode C-MOS input mode; interrupt on rising edges S3F80JB Set1 Bank0...

  • Page 88: P0Int Port 0 External Interrupt Enable Register

    S3F80JB P0INT — Port 0 External Interrupt Enable Register Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode P0.7 External Interrupt (INT4) Enable Bit P0.6 External Interrupt (INT4) Enable Bit P0.5 External Interrupt (INT4) Enable Bit P0.4 External Interrupt (INT4) Enable Bit P0.3 External Interrupt (INT3) Enable Bit...

  • Page 89: P0Pnd Port 0 External Interrupt Pending Register

    No P0.2 external interrupt pending (when read) P0.2 external interrupt is pending (when read) No P0.1 external interrupt pending (when read) P0.1 external interrupt is pending (when read) No P0.0 external interrupt pending (when read) P0.0 external interrupt is pending (when read) S3F80JB Set1 Bank0...

  • Page 90: P0Pur Port 0 Pull-Up Resistor Enable Register

    S3F80JB P0PUR — Port 0 Pull-up Resistor Enable Register Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode P0.7 Pull-up Resistor Enable Bit P0.6 Pull-up Resistor Enable Bit P0.5 Pull-up Resistor Enable Bit P0.4 Pull-up Resistor Enable Bit P0.3 Pull-up Resistor Enable Bit...

  • Page 91: P1Conh Port 1 Control Register (High Byte)

    C-MOS input with pull up mode C-MOS input mode Open-drain output mode Push-pull output mode C-MOS input with pull up mode C-MOS input mode Open-drain output mode Push-pull output mode C-MOS input with pull up mode S3F80JB EAH Set1 Bank0...

  • Page 92: P1Conl Port 1 Control Register (Low Byte)

    S3F80JB P1CONL — Port 1 Control Register (Low Byte) Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode .7 and .6 P1.3 Mode Selection Bits .5 and .4 P1.2 Mode Selection Bits .3 and .2 P1.1 Mode Selection Bits .1 and .0...

  • Page 93: P2Conh Port 2 Control Register (High Byte)

    Push-pull output mode C-MOS input mode; interrupt on rising edges C-MOS input mode; interrupt on falling edges C-MOS input mode; interrupt on rising and falling edges Push-pull output mode C-MOS input mode; interrupt on rising edges S3F80JB ECH Set1 Bank0...

  • Page 94: P2Conl Port 2 Control Register (Low Byte)

    S3F80JB P2CONL — Port 2 Control Register (Low Byte) Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode .7 and .6 P2.3/INT8 Mode Selection Bits .5 and .4 P2.2/INT7 Mode Selection Bits .3 and .2 P2.1/INT6 Mode Selection Bits .1 and .0...

  • Page 95: P2Int Port 2 External Interrupt Enable Register

    P2.0 External Interrupt (INT5) Enable Bit 4-28 Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt S3F80JB Set1 Bank0...

  • Page 96: P2Pnd Port 2 External Interrupt Pending Register

    S3F80JB P2PND — Port 2 External Interrupt Pending Register Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode P2.7 External Interrupt (INT9) Pending Flag Bit (see Note) P2.6 External Interrupt (INT9) Pending Flag Bit P2.5 External Interrupt (INT9) Pending Flag Bit P2.4 External Interrupt (INT9) Pending Flag Bit...
  • Page 97 Disable pull-up resistor Enable pull-up resistor Disable pull-up resistor Enable pull-up resistor Disable pull-up resistor Enable pull-up resistor Disable pull-up resistor Enable pull-up resistor Disable pull-up resistor Enable pull-up resistor Disable pull-up resistor Enable pull-up resistor S3F80JB EEH Set1 Bank0...

  • Page 98: P3Con Port 3 Control Register

    S3F80JB P3CON — Port 3 Control Register Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode .7 and .6 Package Selection and Alternative Function Select Bits Others P3.1 Function Selection Bit .4 and .3 P3.1 Mode Selection Bits Function Selection Bit for P3.0 &...

  • Page 99: Each Function Description And Pin Assignment Of P3Con In 42/44 Pin Package

    The port 3 data register, P3, at location E3H, set1, bank0, contains seven bit values which correspond to the following Port 3 pin functions (bit 6 is not used for the S3F80JB: a. Port3, bit 7: carrier signal on (“1”) or off (“0”).

  • Page 100: P345Con Port3[4:5] Control Register

    .5 and .4 P3.4 Mode Selection Bits .3 and .1 Not used for S3F80JB. Port 4 Control Register Selection Bit NOTE: After CPU reset, P3.4 and P3.5 will be Open-drain output mode by the reset value of P345CON register at E1H, Set1, Bank1.

  • Page 101: P4Con Port 4 Control Register

    Push-pull output mode Open-drain output mode Push-pull output mode Open-drain output mode Push-pull output mode Open-drain output mode Push-pull output mode Open-drain output mode Push-pull output mode Open-drain output mode Push-pull output mode Open-drain output mode Push-pull output mode S3F80JB Set1 Bank0...

  • Page 102: P4Conh Port 4 Control Register (High Byte)

    S3F80JB P4CONH — Port 4 Control Register (High Byte) Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode .7 and .6 P4.7 Mode Selection Bits .5 and .4 P4.6 Mode Selection Bits .3 and .2 P4.5 Mode Selection Bits .1 and .0...

  • Page 103: P4Conl Port 4 Control Register (Low Byte)

    Push-pull output mode C-MOS input with pull up mode C-MOS input mode Open-drain output mode Push-pull output mode C-MOS input with pull up mode C-MOS input mode Open-drain output mode Push-pull output mode C-MOS input with pull up mode S3F80JB Set1 Bank1...

  • Page 104: Pp Register Page Pointer

    Source Register Page Selection Bits NOTE: In the S3F80JB microcontroller, a paged expansion of the internal register file is not implemented. For this reason, only page 0 settings are valid. Register page pointer values for the source and destination register page are automatically set to ‘0000B’...

  • Page 105: Rp0 Register Pointer 0

    8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1,bank0, selecting the 8-byte working register slice C0H–C7H. .2 – .0 Not used for S3F80JB. — Register Pointer 1 Bit Identifier Reset Value...

  • Page 106: Spl Stack Pointer (Low Byte)

    S3F80JB — Stack Pointer (Low Byte) Bit Identifier Reset Value Read/Write Register addressing mode only. Addressing Mode .7 – .0 Stack Pointer Address (Low Byte) The SP value is undefined following a reset. STOPCON — Stop Control Register Bit Identifier...

  • Page 107: Sym System Mode Register

    Global Interrupt Enable Bit NOTES: Because an external interface is not implemented for the S3F80JB, SYM.7 must always be "0". Although the SYM register is not used, SYM.5 should always be “0”. If you accidentally write a “1” to this bit during normal operation, a system malfunction may occur.
  • Page 108 S3F80JB T0CON — Timer 0 Control Register Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode .7 – .6 Timer 0 Input Clock Selection Bits .5 and .4 Timer 0 Operating Mode Selection Bits Timer 0 Counter Clear Bit...

  • Page 109: T1Con Timer 1 Control Register

    Enable T1 overflow interrupt Disable T1 match/capture interrupt Enable T1 match/capture interrupt No T1 match/capture interrupt pending (when read) Clear T1 match/capture interrupt pending condition (when write) T1 match/capture interrupt is pending (when read) No effect (when write) S3F80JB FAH Set1 Bank0...

  • Page 110: T2Con Timer 2 Control Register

    S3F80JB T2CON — Timer 2 Control Register Bit Identifier Reset Value Read/Write Register addressing mode only Addressing Mode .7 and .6 Timer 2 Input Clock Selection Bits .5 and .4 Timer 2 Operating Mode Selection Bits Timer 2 Counter Clear Bit...

  • Page 111: Chapter 5 Interrupt Structure

    128. (The actual number of vectors used for S3C8/S3F8-series devices is always much smaller.) If an interrupt level has more than one vector address, the vector priorities are set in hardware. The S3F80JB uses eighteen vectors. Two vector addresses are shared by four interrupt sources.

  • Page 112: Interrupt Types

    ) + one source (S ) + multiple sources (S – V ) + multiple sources (S Vectors IRQn IRQn IRQn The number of S and V value is expandable. Figure 5-1. S3C8/S3F8-Series Interrupt Types – S – S – S Sources S3F80JB...
  • Page 113 S3F80JB INTERRUPT STRUCTURE The S3F80JB microcontroller supports twenty-four interrupt sources. Sixteen of the interrupt sources have a corresponding interrupt vector address; the remaining eight interrupt sources share by two vector address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2.

  • Page 114: S3F80Jb Interrupt Structure

    P2.6 external interrupt P2.5 external interrupt P2.4 external interrupt P0.3 external interrupt P0.2 external interrupt P0.1 external interrupt P0.0 external interrupt P0.7 external interrupt P0.6 external interrupt P0.5 external interrupt P0.4 external interrupt Figure 5-2. S3F80JB Interrupt Structure S3F80JB Reset/Clear...

  • Page 115: Interrupt Vector Addresses

    S3F80JB INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3F80JB interrupt structure are stored in the vector address area of the internal program memory ROM, 00H–FFH (See Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).

  • Page 116: S3F80Jb Interrupt Vectors

    The priorities within a given level are fixed in hardware. Reset (Basic timer overflow or POR) interrupt vector address can be changed by smart option (Refer to Table 15-3 or Figure 2-2). Table 5-1. S3F80JB Interrupt Vectors Interrupt Source Basic timer overflow/POR...

  • Page 117: Enable/Disable Interrupt Instructions (Ei, Di)

    IRQ0–IRQ7. Controls the relative processing priorities of the interrupt levels. The eight levels of the S3F80JB are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.

  • Page 118: Interrupt Processing Control Points

    (register pointer) information. nRESET IRQ0-IRQ7 Interrupts NOTE Interrupt Request Register (Read-only) Interrupt Priority Register Interrupt Mask Figure 5-4. Interrupt Function Diagram Polling Cycle Register Global Interrupt Control (EI, DI or SYM.0 manipulation) S3F80JB Vector Interrupt Cycle...

  • Page 119: Peripheral Interrupt Control Registers

    S3F80JB PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral (See Table 5-3). Table 5-3. Vectored Interrupt Source Control and Data Registers...

  • Page 120: System Mode Register (Sym)

    0 = Normal operation (Tri-state disabled) 1 = High impedance (Tri-state enabled) NOTE: In case of S3F80JB, an external memory interface is not implemented. 5-10 System Mode Register (SYM) DEH, Set 1, Bank 0, R/W Not used Fast Interrupt Level...

  • Page 121: Interrupt Mask Register (Imr)

    S3F80JB INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (DDH, Set 1, Bank0) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine.

  • Page 122: Interrupt Priority Register (Ipr)

    4. IPR.3 defines the possible subgroup B relationships. IPR.2 controls interrupt group B. — IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts. 5-12 Group B IRQ2 IRQ3 IRQ4 Figure 5-7. Interrupt Request Priority Groups Group C IRQ5 IRQ6 IRQ7 S3F80JB...

  • Page 123: Interrupt Priority Register (Ipr)

    S3F80JB Group Priority: D7 D4 D1 = Undefined = B > C > A = A > B > C = B > A > C = C > A > B = C > B > A = A > C > B...

  • Page 124: Interrupt Request Register (Irq)

    INTERRUPT STRUCTURE S3F80JB INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (DCH, Set 1, Bank0), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on.

  • Page 125: Interrupt Pending Function Types

    "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software. In the S3F80JB interrupt structure, the timer 0 overflow interrupt (IRQ0), the timer 1 overflow interrupt (IRQ1), the timer 2 overflow interrupt (IRQ3), and the counter A interrupt (IRQ2) belong to this category of interrupts whose pending condition is cleared automatically by hardware.

  • Page 126: Interrupt Source Polling Sequence

    INTERRUPT STRUCTURE S3F80JB INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source.

  • Page 127: Generating Interrupt Vector Addresses

    S3F80JB GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (except smart option ROM Cell- 003CH, 003DH, 003EH and 003FH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1.
  • Page 128 — When a fast interrupt occurs, the contents of the FLAGS register are stored in an unmapped, dedicated register called FLAGS' (“FLAGS prime”). For the S3F80JB microcontroller, the service routine for any one of the eight interrupt levels: IRQ0–IRQ7, can be selected for fast interrupt processing.

  • Page 129: Chapter 6 Instruction Set

    S3F80JB INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: —...

  • Page 130: Instruction Group Summary

    Load program memory with pre-decrement Load external data memory with pre-increment Load program memory with pre-increment Load word Pop from stack Pop user stack (decrementing) Pop user stack (incrementing) Push to stack Push user stack (decrementing) Push user stack (incrementing) S3F80JB Instruction...
  • Page 131 S3F80JB Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Arithmetic Instructions dst,src dst,src dst,src DECW dst,src INCW MULT dst,src dst,src dst,src Logic Instructions dst,src dst,src dst,src Instruction Add with carry Compare Decimal adjust Decrement Decrement word Divide Increment Increment word...
  • Page 132 Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Next Return Wait for interrupt Bit AND Bit compare Bit complement Bit reset Bit set Bit OR Bit XOR Test complement under mask Test under mask S3F80JB...
  • Page 133 S3F80JB Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Rotate and Shift Instructions SWAP CPU Control Instructions IDLE SRP0 SRP1 STOP Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag...

  • Page 134: Flags Register (Flags)

    Zero flag (Z) Sign flag (S) System Flags Register (FLAGS) D5H, Set 1, Bank0 , R/W Overflow (V) Figure 6-1. System Flags Register (FLAGS) Bank address status flag (BA) First interrupt status flag (FIS) Half-carry flag (H) Decimal adjust flag (D) S3F80JB...

  • Page 135: Flag Descriptions

    S3F80JB FLAG DESCRIPTIONS Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.

  • Page 136: Instruction Set Notation

    Table 6-3. Instruction Set Symbols Description Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register (D5H) Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode S3F80JB...

  • Page 137: Instruction Notation Conventions

    S3F80JB Notation Description Condition code Working register only Bit (b) of working register Bit 0 (LSB) of working register Working register pair Register or working register Bit 'b' of register or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)

  • Page 138: Opcode Quick Reference

    R1,IM R2,R1 IR2,R1 R1,IM RR2,RR1 IR2,RR1 RR1,IML CALL IR1,IM R2,R1 R2,IR1 R1,IM CALL CALL IRR1 IR2,R1 S3F80JB r0–Rb r1.b, R2 BXOR r0–Rb BTJR r2.b, RA r0–Rb BITC r1.b BAND r0–Rb r1.b r1, x, r2 r2, x, r1 r1, Irr2, xL...
  • Page 139 S3F80JB Table 6-5. Opcode Quick Reference (Continued) – r1,R2 r2,R1 ↓ ↓ ↓ r1,R2 r2,R1 OPCODE MAP LOWER NIBBLE (HEX) DJNZ r1,RA cc,RA ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ DJNZ r1,RA cc,RA INSTRUCTION SET r1,IM cc,DA ↓...

  • Page 140: Condition Codes

    Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal S3F80JB Flags Set – – C = 1 C = 0 Z = 1 Z = 0...

  • Page 141: Instruction Descriptions

    S3F80JB INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: —...

  • Page 142: Adc Add With Carry

    R1 = 14H, R2 = 03H → R1 = 1BH, R2 = 03H → Register 01H = 24H, register 02H = 03H → Register 01H = 2BH, register 02H = 03H → Register 01H = 32H S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 143: Add Add

    S3F80JB — Add dst,src dst ← dst + src Operation: The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is a carry from the most significant bit of the result; cleared otherwise.

  • Page 144: And Logical And

    R1 = 02H, R2 = 03H → R1 = 02H, R2 = 03H → Register 01H = 01H, register 02H = 03H → Register 01H = 00H, register 02H = 03H → Register 01H = 21H S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 145: Band Bit And

    S3F80JB BAND — Bit AND BAND dst,src.b BAND dst.b,src dst(0) ← dst(0) AND src(b) Operation: dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected.

  • Page 146: Bcp Bit Compare

    (01H) and bit zero of the destination register (R1). Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H). 6-18 Bytes → R1 = 07H, register 01H = 01H S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 147: Bitc Bit Complement

    S3F80JB BITC — Bit Complement BITC dst.b dst(b) ← NOT dst(b) Operation: This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise.

  • Page 148: Bitr Bit Reset

    R1.1 If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B). 6-20 → R1 = 05H Bytes Cycles Opcode (Hex) S3F80JB Addr Mode...

  • Page 149: Bits Bit Set

    S3F80JB BITS — Bit Set BITS dst.b dst(b) ← 1 Operation: The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: dst | b | 1 NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
  • Page 150 ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in register 01H. 6-22 Bytes → R1 = 07H, register 01H = 03H → Register 01H = 07H, R1 = 07H S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 151: Btjrf Bit Test, Jump Relative On False

    S3F80JB BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b If src(b) is a "0", then PC ← PC + dst Operation: The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC;...

  • Page 152: Btjrt Bit Test, Jump Relative On True

    (R1). Because it is a "1", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.) 6-24 Bytes S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 153: Bxor Bit Xor

    S3F80JB BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src dst(0) ← dst(0) XOR src(b) Operation: dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected.

  • Page 154: Call Call Procedure

    (Memory locations 0000H = 1AH, 0001H = 4AH, where 4AH is the address that follows the instruction.) SP = 0000H (0000H = 1AH, 0001H = 49H) → SP = 0000H (0000H = 1AH, 0001H = 49H) Bytes Cycles Opcode (Hex) S3F80JB Addr Mode...

  • Page 155: Ccf Complement Carry Flag

    S3F80JB — Complement Carry Flag C ← NOT C Operation: The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.

  • Page 156: Clr Clear

    00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H. 6-28 → Register 00H = 00H Register 01H = 02H, register 02H = 00H Bytes Cycles Opcode (Hex) S3F80JB Addr Mode...

  • Page 157: Com Complement

    S3F80JB — Complement dst ← NOT dst Operation: The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise.

  • Page 158: Cp Compare

    JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3. 6-30 R1,R2 → Set the C and S flags R1,R2 UGE,SKIP R3,R1 Bytes Cycles Opcode (Hex) S3F80JB Addr Mode...

  • Page 159: Cpije Compare, Increment, And Jump On Equal

    S3F80JB CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA If dst – src = "0", PC ← PC + RA Operation: Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter.

  • Page 160: Cpijne Compare, Increment, And Jump On Non-Equal

    SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to – 128.) 6-32 Bytes R2 = 04H, PC jumps to SKIP location Cycles Opcode (Hex) S3F80JB Addr Mode...

  • Page 161: Da Decimal Adjust

    S3F80JB — Decimal Adjust dst ← DA dst Operation: The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not...

  • Page 162: Da Decimal Adjust

    0 1 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0 1 1 0 0 0 1 0 C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = 1 @R1 ← 31–0 S3F80JB...

  • Page 163: Dec Decrement

    S3F80JB — Decrement dst ← dst – 1 Operation: The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise.

  • Page 164: Decw Decrement Word

    To avoid this problem, we recommend that you use DECW as shown in the following example: LOOP: DECW RR0 6-36 → R0 = 12H, R1 = 33H → Register 30H = 0FH, register 31H = 20H R2,R1 R2,R0 NZ,LOOP Bytes Cycles Opcode (Hex) S3F80JB Addr Mode...
  • Page 165 S3F80JB — Disable Interrupts SYM (0) ← 0 Operation: Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.

  • Page 166: Div Divide (Unsigned)

    = "0"; cleared otherwise. Bytes → R0 = 03H, R1 = 40H → R0 = 03H, R1 = 20H → R0 = 03H, R1 = 80H S3F80JB –1; cleared otherwise. Cycles Opcode Addr Mode (Hex) 26/10 26/10...

  • Page 167: Djnz Decrement And Jump If Non-Zero

    S3F80JB DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst r ← r – 1 Operation: If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC.

  • Page 168: Ei Enable Interrupts

    If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global interrupt processing.) 6-40 Bytes Cycles Opcode (Hex) S3F80JB...

  • Page 169: Enter Enter

    S3F80JB ENTER — Enter ENTER ← Operation: ← ← ← ← This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer.

  • Page 170: Exit Exit

    Address 0040 0022 Data Stack 6-42 SP + 2 IP + 2 Address Data PCL old Exit Memory Bytes Cycles 14 (internal stack) 16 (internal stack) After Data 0052 Address 0060 Main 0022 Memory Data Stack S3F80JB Opcode (Hex) Data...

  • Page 171: Idle Idle Operation

    S3F80JB IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected.

  • Page 172: Inc Increment

    In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H. 6-44 → R0 = 1CH → Register 00H = 0DH → R0 = 1BH, register 01H = 10H Bytes Cycles Opcode (Hex) r = 0 to F S3F80JB Addr Mode...

  • Page 173: Incw Increment Word

    S3F80JB INCW — Increment Word INCW dst ← dst + 1 Operation: The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one.

  • Page 174: Iret Interrupt Return

    (as with a reset of the IPR register). 6-46 IRET (Fast) PC ↔ IP FLAGS ← FLAGS' FIS ← 0 Bytes Bytes IRET 100H Interrupt Service Routine JP to FFH FFFFH S3F80JB Cycles Opcode (Hex) 10 (internal stack) 12 (internal stack) Cycles Opcode (Hex)

  • Page 175: Jp Jump

    S3F80JB — Jump cc,dst (Conditional) (Unconditional) If cc is true, PC ← dst Operation: The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed.

  • Page 176: Jr Jump Relative

    If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed. 6-48 Bytes → PC = 1FF7H S3F80JB Cycles Opcode Addr Mode (Hex) cc = 0 to F...

  • Page 177: Ld Load

    S3F80JB — Load dst,src dst ← src Operation: The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: dst | opc src | opc Bytes dst | src dst | src...
  • Page 178 Register 00H = 0AH → Register 00H = 01H, register 01H = 10H → Register 00H = 01H, register 01H = 02, register 02H = 02H R0 = 0FFH, R1 = 0AH Register 31H = 0AH, R0 = 01H, R1 = 0AH S3F80JB...

  • Page 179: Ldb Load Bit

    S3F80JB — Load Bit dst,src.b dst.b,src dst(0) ← src(b) Operation: dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected.

  • Page 180: Ldc/Lde Load Memory

    The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory. 6-52 Bytes S3F80JB Cycles Opcode Addr Mode...

  • Page 181: Ldc/Lde Load Memory

    S3F80JB LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory...

  • Page 182: Ldcd/Lded Load Memory And Decrement

    ; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ← RR6 – 1) ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is decremented by one (RR6 ← RR6 – 1) ; R8 = 0DDH, R6 = 10H, R7 = 32H S3F80JB Opcode Addr Mode (Hex)

  • Page 183: Ldci/Ldei Load Memory And Increment

    S3F80JB LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src dst ← src Operation: rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair.
  • Page 184 ; R0 = 77H, R6 = 2FH, R7 = 0FFH ; (RR6 ← RR6 – 1) ; 77H (contents of R0) is loaded into external data memory ; location 2FFFH (3000H – 1H) ; R0 = 77H, R6 = 2FH, R7 = 0FFH S3F80JB Opcode Addr Mode (Hex)

  • Page 185: Ldcpi/Ldepi Load Memory With Pre-Increment

    S3F80JB LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src rr ← rr + 1 Operation: dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented.

  • Page 186: Ldw Load Word

    02H = 03H, register 03H = 0FH → R2 = 03H, R3 = 0FH, → Register 04H = 03H, register 05H = 0FH → R6 = 12H, R7 = 34H → Register 02H = 0FH, register 03H = 0EDH S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 187: Mult Multiply (Unsigned)

    S3F80JB MULT — Multiply (Unsigned) MULT dst,src dst ← dst × src Operation: The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address.

  • Page 188: Next Next

    The following diagram shows one example of how to use the NEXT instruction. Before Address Data 0043 Address 0120 6-60 Bytes Address 0045 Data Data 0130 Address H Address L Address H Next Memory S3F80JB Cycles Opcode (Hex) After Data Address Data Address H Address L Address H Routine Memory...

  • Page 189: Nop No Operation

    S3F80JB — No Operation Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format:...

  • Page 190: Or Logical Or

    R0 = 3FH, R1 = 2AH → R0 = 37H, R2 = 01H, register 01H = 37H → Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH → Register 00H = 0AH S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 191: Pop Pop From Stack

    S3F80JB — Pop From Stack dst ← @SP Operation: SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected.

  • Page 192: Popud Pop User Stack (Decrementing)

    "POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The user stack pointer is then decremented by one, leaving the value 41H. 6-64 Bytes → Register 00H = 41H, register 02H = 6FH, register 42H = 6FH S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 193: Popui Pop User Stack (Incrementing)

    S3F80JB POPUI — Pop User Stack (Incrementing) POPUI dst,src dst ← src Operation: IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented.

  • Page 194: Push Push To Stack

    Register 40H = 4FH, stack register 0FFH = 4FH, SPH = 0FFH, SPL = 0FFH → Register 40H = 4FH, register 4FH = 0AAH, stack register 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH S3F80JB Opcode Addr Mode (Hex)

  • Page 195: Pushud Push User Stack (Decrementing)

    S3F80JB PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src IR ← IR – 1 Operation: dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer.

  • Page 196: Pushui Push User Stack (Incrementing)

    "PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H register value, 05H, is then loaded into the location addressed by the incremented user stack pointer. 6-68 Bytes Register 00H = 04H, register 01H = 05H, register 04H = 05H S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 197: Rcf Reset Carry Flag

    S3F80JB — Reset Carry Flag C ← 0 Operation: The carry flag is cleared to logic zero, regardless of its previous value. Flags: Cleared to "0". No other flags are affected. Format: Example: Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.

  • Page 198: Ret Return

    The stack pointer then pops the value in location 00FEH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 00FEH. 6-70 Bytes PC = 101AH, SP = 00FEH S3F80JB Cycles Opcode (Hex) 8 (internal stack) 10 (internal stack)

  • Page 199: Rl Rotate Left

    S3F80JB — Rotate Left C ← dst (7) Operation: dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.

  • Page 200: Rlc Rotate Left Through Carry

    (01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag. 6-72 Bytes → Register 00H = 54H, C = "1" → Register 01H = 02H, register 02H = 2EH, C = "0" S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 201: Rr Rotate Right

    S3F80JB — Rotate Right C ← dst (0) Operation: dst (7) ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

  • Page 202: Rrc Rotate Right Through Carry

    2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0". 6-74 Bytes → Register 00H = 2AH, C = "1" → Register 01H = 02H, register 02H = 0BH, C = "1" S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 203: Sb0 Select Bank 0

    S3F80JB — Select Bank 0 BANK ← 0 Operation: The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected.

  • Page 204: Sb1 Select Bank 1

    1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some KS88-series microcontrollers.) Flags: No flags are affected. Format: Example: The statement sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented. 6-76 Bytes Cycles Opcode (Hex) S3F80JB...

  • Page 205: Sbc Subtract With Carry

    S3F80JB — Subtract With Carry dst,src dst ← dst – src – c Operation: The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected.

  • Page 206: Scf Set Carry Flag

    The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Example: The statement sets the carry flag to logic one. 6-78 Bytes Cycles Opcode (Hex) S3F80JB...

  • Page 207: Sra Shift Right Arithmetic

    S3F80JB — Shift Right Arithmetic dst (7) ← dst (7) Operation: C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag.

  • Page 208: Srp/Srp0/Srp1

    The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to 68H. 6-80 — Set Register Pointer RP0 (3) RP1 (4–7) RP1 (3) ← src (3–7) ← src (3–7) ← src (4–7), ← ← src (4–7), ← Bytes Cycles Opcode (Hex) S3F80JB Addr Mode...

  • Page 209: Stop Stop Operation

    S3F80JB STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts.

  • Page 210: Sub Subtract

    Register 01H = 1EH, register 02H = 03H Register 01H = 17H, register 02H = 03H → Register 01H = 91H; C, S, and V = "1" → Register 01H = 0BCH; C and S = "1", V = "0" S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 211: Swap Swap Nibbles

    S3F80JB SWAP — Swap Nibbles SWAP dst (0 – 3) ↔ dst (4 – 7) Operation: The contents of the lower four bits and upper four bits of the destination operand are swapped. Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise.

  • Page 212: Tcm Test Complement Under Mask

    Register 00H = 2BH, register 01H = 02H, Z = "1" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1" → Register 00H = 2BH, Z = "0" S3F80JB Cycles Opcode Addr Mode (Hex)

  • Page 213: Tm Test Under Mask

    S3F80JB — Test Under Mask dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand.

  • Page 214: Wfi Wait For Interrupt

    The following sample program structure shows the sequence of operations that follow a "WFI" statement: 6-86 Bytes Main program (Enable global interrupt) (Wait for interrupt) (Next instruction) Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed S3F80JB Cycles Opcode (Hex) n = 1, 2, 3, … )

  • Page 215: Xor Logical Exclusive Or

    S3F80JB — Logical Exclusive OR dst,src dst ← dst XOR src Operation: The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different;...

  • Page 216: System Clock Circuit

    CLOCK CIRCUITS OVERVIEW The clock frequency for the S3F80JB can be generated by an external crystal or supplied by an external clock source. The clock frequency for the S3F80JB can range from 1MHz to 8 MHz. The maximum CPU clock frequency, as determined by CLKCON register, is 8 MHz.

  • Page 217: Clock Status During Power-Down Modes

    Oscillator Wake-up NOTES: An external interrupt with an RC-delay noise filter (for the S3F80JB INT0-9) is fixed to release stop mode and "wake up" the main oscillator. Because the S3F80JB has no subsystem clock, the 3-bit CLKCON signature code (CLKCON.2-CLKCON.0) is no meaning.

  • Page 218: System Clock Control Register (Clkcon)

    — Oscillator frequency divide-by value The CLKCON.7 - .5 and CLKCON.2- .0 Bit are not used in S3F80JB. After a reset, the main oscillator is activated, and the f (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the...

  • Page 219: Reset Sources

    During reset, most control and status are forced to initial values and the program counter is loaded from the reset vector. In case of S3F80JB, reset vector can be changed by smart option. (Refer to the page 2-3 or 15-5).

  • Page 220: Reset Sources Of The S3F80Jb

    5. When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’ and chip is in stop mode, external interrupt input by P0 and P2 regardless of external interrupt enable/disable generates the reset signal. Figure 8-1. RESET Sources of The S3F80JB S3F80JB...

  • Page 221: Reset Block Diagram Of The S3F80Jb

    IPOR / LVD Control Bit '1' smart option bit[7] @03FH P0&P2 Noise (INT0~INT9) Filter IPOR / LVD Control Bit '1' smart option bit[7] @03FH Figure 8-2. RESET Block Diagram of The S3F80JB Enable/ Disable Disable /Enable IPOR (WDT) Noise Reset Pulse...

  • Page 222: Reset Mechanism

    LVD RESET The Low Voltage Detect Circuit (LVD) is built on the S3F80JB product to generate a system reset when IPOR/LVD Control Bit of smart option is set to ‘1’ regardless of operation mode. So if IPOR / LVD Control Bit of smart option is set to ‘1’...

  • Page 223: Internal Power-On Reset

    STOP mode, the other is not STOP mode. 5. In S3F80JB, one between LVD and IPOR is selected as reset source by IPOR / LVD Control Bit setting value of smart option in the stop mode. If the setting value is ‘0’, LVD can be disabled by STOP instruction.

  • Page 224: Timing Diagram For Internal Power-On Reset Circuit

    ‘0’, the system reset by LVD circuit doesn’t occur in stop mode. Refer to page 2-3 relating to the smart option. The rising time of VDD must be less than 1ms. If not, IPOR can’t detect power on reset. = 1ms Rising Time) = 0.85 V = 0.4 V Reset Pulse Width NOTE S3F80JB Reset pulse Time...

  • Page 225: External Interrupt Reset

    0.4V NOTE: Figure 8-6. Reset Timing Diagram for The S3F80JB in STOP mode by IPOR EXTERNAL INTERRUPT RESET When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’and chip is in stop mode, if external interrupt is occurred by among the enabled external interrupt sources, from INT0 to INT9, reset signal is generated.

  • Page 226: Stop Error Detection & Recovery

    Vreset < V Transition from “Vreset < V ” to “V < Vreset” Transition from “Vreset < V ” to “V < Vreset” S3F80JB Reset System Reset Source LVD circuit System reset occurs – No system reset – No system reset...

  • Page 227: Power-Down Modes

    S3F80JB POWER-DOWN MODES The power down mode of S3F80JB are described following that: — Idle mode — Back- up mode — Stop mode IDLE MODE Idle mode is invoked by the instruction IDLE (op-code 6FH). In Idle mode, CPU operations are halted while some peripherals remain active.

  • Page 228: Back-Up Mode

    RESET BACK-UP MODE For reducing current consumption, S3F80JB goes into Back-up mode. If external reset pin is low state or a falling level of V is detected by LVD circuit on the point of V peripheral operation were stopped due to oscillation stop, the supply current is reduced. In back-up mode, chip cannot be released from stop state by any interrupt.

  • Page 229: Stop Mode

    S3F80JB STOP MODE STOP mode is invoked by executing the instruction ‘STOP’, after setting the stop control register (STOPCON). In STOP mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the current consumption can be reduced.

  • Page 230: Sources To Release Stop Mode

    ‘0’ and external interrupt is enabled, S3F80JB is released stop mode and generated reset signal. On the other hand, when IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, S3F80JB is only released stop mode and isn’t generated reset signal.
  • Page 231 Port0 or P2.4-P2.7, S3F80JB is released stop mode and generate reset signal. On the other hand, when IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, S3F80JB is only released stop mode. Reset doesn’t occur. When the falling edge of a pin on Port0 and P2.4-P2.7 is entered, the chip is released from stop mode even though external interrupt is disabled.

  • Page 232: System Reset Operation

    System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal CPU and peripheral modules. This procedure brings the S3F80JB into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level for a minimum time interval after the power supply comes within tolerance.

  • Page 233: Hardware Reset Values

    S3F80JB HARDWARE RESET VALUES Tables 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: — A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
  • Page 234 You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB. 8-16 Mnemonic Address P1CONH P1CONL P2CONH P2CONL P2PUR P3CON P4CON P0INT P0PND CACON CADATAH CADATAL T1CNTH T1CNTL T1DATAH T1DATAL T1CON STOPCON Locations FCH is not mapped. ( For factory test ) BTCNT Bit Values After Reset S3F80JB –...

  • Page 235: Set 1, Bank 1 Register Values After Reset

    P345CON will be initialized as “50H” to set P3.4 and P3.5 into open drain output mode after reset operation. S3F80JB has P4CONH, P4CONL and P4CON as port4 control registers. P4CONH and P4CONL will be initialized as the C-MOS input with pull up mode after reset. On the other hand, P4CON will be initialized as open-drain output mode.

  • Page 236: Reset Generation According To The Condition Of Smart Option

    External ISR P0 & P2.4-2.7 STOP Release and Continue P2.0-2.3 STOP NOTES Smart option7th bit @3FH Reset Reset Continue Reset External ISR Continue Reset STOP STOP Release and Reset STOP STOP Release and Reset STOP Release and Reset STOP S3F80JB...

  • Page 237: Recommendation For Unusued Pins

    S3F80JB RECOMMENDATION FOR UNUSUED PINS To reduce overall power consumption, please configure unused pins according to the guideline description Table 8-6. Table 8-6. Guideline for Unused Pins to Reduced Power Consumption Pin Name • Port 0 Set Input mode •...

  • Page 238: Summary Table Of Back-Up Mode, Stop Mode, And Reset Status

    STOP ( LD STOPCON,#0A5H ) ( STOP) • All port is keep the previous status. • Output port data is not changed. – • External interrupt, or reset • SED & R Circuit. • It depends on control program S3F80JB...

  • Page 239: Overview

    I/O PORTS OVERVIEW The S3F80JB microcontroller has two kinds of package and different I/O number relating to the package type: 44-QFP package has five bit-programmable I/O ports, P0–P3 and P4. Four ports, P0–P2 and P4, are 8-bit ports and P3 is a 6-bit port. This gives a total of 38 I/O pins.

  • Page 240: S3F80Jb Port Configuration Overview (44-Qfp)

    I/O PORTS Table 9-1. S3F80JB Port Configuration Overview (44-QFP) Port Port 0 8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable register (P0INT) and pending control register (P0PND);...

  • Page 241: S3F80Jb Port Configuration Overview (32-Sop)

    S3F80JB Table 9-3. S3F80JB Port Configuration Overview (32-SOP) Port Port 0 8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable register (P0INT) and pending control register (P0PND);...

  • Page 242: Port Data Registers

    I/O PORTS PORT DATA REGISTERS Table 9-4 gives you an overview of the register locations of all four S3F80JB I/O port data registers. Data registers for ports 0,1,2 and 4 have the general format shown in Figure 9-1. The data register for port 3, P3, contains 6-bits for P3.0–P3.5, and an additional status bit (P3.7) for carrier signal on/off.

  • Page 243: Pull-Up Resistor Enable Registers (Port 0 And Port 2 Only)

    S3F80JB PULL-UP RESISTOR ENABLE REGISTERS You can assign pull-up resistors to the pin circuits of individual pins in port0 and port2. To do this, you make the appropriate settings to the corresponding pull-up resistor enable registers; P0PUR and P2PUR. These registers are located in set 1, bank 0 at locations E7H and EEH, respectively, and are read/write accessible using Register addressing mode.

  • Page 244: Basic Timer (Bt)

    S3F80JB BASIC TIMER and TIMER 0 OVERVIEW The S3F80JB has two default timers: the 8-bit basic timer and the 8-bit general-purpose timer/counter. The 8-bit timer/counter is called timer 0. BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: —...

  • Page 245: Basic Timer Control Register (Btcon)

    1 = Clear both dividers Basic Timer Counter Clear Bits: 0 = No effect 1 = Clear BTCNT Basic Timer Input Clock Selection Bits: 00 = f /4096 01 = f /1024 10 = f /128 11 = Invalid selection S3F80JB...

  • Page 246: Basic Timer Function Description

    S3F80JB BASIC TIMER FUNCTION DESCRIPTION Watch-dog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than '1010B'. (The '1010B' value disables the watch-dog function.) A reset clears BTCON to '00H', automatically enabling the watch-dog timer function.

  • Page 247: Timer 0 Control Register (T0Con)

    BASIC TIMER and TIMER 0 S3F80JB TIMER 0 CONTROL REGISTER (T0CON) You use the timer 0 control register, T0CON, to — Select the timer 0 operating mode (interval timer, capture mode, or PWM mode) — Select the timer 0 input clock frequency —...

  • Page 248: Timer 0 Data Register (T0Data)

    S3F80JB Timer 0 Input Clock Selection Bits: 00 = f /4096 01 = f /256 10 = f (NOTE) 11 = External clock Timer 0 Operating Mode Selection Bits: 01 = Capture mode (capture on rising edge, counter running, OVF can occur)

  • Page 249: Timer 0 Function Description

    With each match, the level of the signal at the timer 0 output pin is inverted (See Figure 10-4). 8-Bit Counter (T0CNT) 8-Bit Comparator Buffer Register Timer0 Data Register (T0DATA) Figure 10-4. Simplified Timer 0 Function Diagram: Interval Timer Mode 10-6 IRQ0(T0INT) Pending (T0CON.0) Interrupt Enable/Disable (T0CON.1) T0CON.3 R (Clear) Match Match Signal T0CON.3 S3F80JB P3.0/T0CAP T0CON.5 T0CON.4...

  • Page 250: Simplified Timer 0 Function Diagram: Pwm Mode

    S3F80JB Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register.

  • Page 251: Simplified Timer 0 Function Diagram: Capture Mode

    (duration) of the signal that is being input at the T0CAP pin (See Figure 10-6). P3.0/T0CAP T0CON.5 T0CON.4 Figure 10-6. Simplified Timer 0 Function Diagram: Capture Mode 10-8 Interrupt Enable/Disable (T0CON.2) 8-bit Counter Pending (T0CNT) Pending Interrupt Enable/Disable (T0CON.1) Timer 0 Data Register (T0DATA) S3F80JB IRQ0 (T0OVF) IRQ0 (T0INT)

  • Page 252: Basic Timer And Timer 0 Block Diagram

    S3F80JB 1/4096 1/1024 1/128 Bit 0 1/4096 1/256 P3.1/T0CK P3.2/T0CK (note 3) P3.0/T0CAP Bits 5, 4 NOTES: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).

  • Page 253: Configuring The Basic Timer

    ; Disable global and fast interrupts ; Stack pointer low byte → "0" ; Stack area starts at 0FFH ; Set register pointer → 0C0H ; Enable interrupts ; Basic timer clock: f /4096 ; Clear basic timer counter S3F80JB...
  • Page 254 S3F80JB PROGRAMMING TIP — Programming Timer 0 This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows: —...

  • Page 255: Programming Timer 0

    PROGRAMMING TIP — Programming Timer 0 (Continued) R0,#32H ULT,NO_200MS_SET BITS R1.2 NO_200MS_SET: T0CON,#42H T0OVER IRET 10-12 ; 50 × 4 = 200 ms ; Bit setting (61.2H) ; Clear pending bit ; Restore register pointer 0 value ; Return from interrupt service routine S3F80JB...

  • Page 256: Overview

    44 package; at the P3.0 for 32 package (You can select a rising edge, a falling edge, or both edges as the trigger). In the S3F80JB interrupt structure, the Timer 1 overflow interrupt has higher priority than the Timer 1 match or capture interrupt.

  • Page 257: Timer 1 Overflow Interrupt

    P3.0 is assigned as T1CAP function for 32 pin package and P3.3 is assigned as T1CAP function for 44 pin package. Figure 11-1. Simplified Timer 1 Function Diagram: Capture Mode 11-2 16-Bit Up Counter Timer 1 Data T1CON.5 T1CON.4 T1CON.2 IRQ1 (T1OVF) Pending IRQ1 (T1CON.0) (T1INT) Interrupt Enable/Disable (T1CON.1) S3F80JB...

  • Page 258: Timer 1 Match Interrupt

    S3F80JB TIMER 1 MATCH INTERRUPT Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value matches the value that is written to the Timer 1 reference data registers, T1DATAH and T1DATAL. When a match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and up counting resumes from ‘00H’.

  • Page 259: Timer 1 Block Diagram

    16-Bit Compatator T1CON.5-.4 Timer 1 High/Low Buffer Register T1CON.3 Match Signal T1OVF Timer 1 Data High/Low Register Data Bus Match signal is occurrd only in interval mode. Figure 11-3. Timer 1 Block Diagram T1CON.2 IRQ1 T1CON.3 (note) T1CON.1 T1CON.0 IRQ1 S3F80JB...

  • Page 260: Timer 1 Control Register (T1Con)

    S3F80JB TIMER 1 CONTROL REGISTER (T1CON) The Timer 1 control register, T1CON, is located in Set 1, FAH, Bank0 and is read/write addressable. T1CON contains control settings for the following T1 functions: — Timer 1 input clock selection — Timer 1 operating mode selection —...

  • Page 261: Timer 1 Registers (T1Cnth, T1Cntl, T1Datah, T1Datal)

    F7H, Set 1, Bank 0, R Timer 1 Data High-byte Register (T1DATAH) F8H, Set 1, Bank 0, R/W Timer 1 Data Low-byte Register (T1DATAL) F9H, Set 1, Bank 0, R/W Reset Value: 00H Reset Value: 00H Reset Value: FFH Reset Value: FFH S3F80JB...

  • Page 262: Overview

    S3F80JB COUNTER A OVERVIEW The S3F80JB microcontroller has one 8-bit counter called counter A. Counter A, which can be used to generate the carrier frequency, has the following components (See Figure 12-1): — Counter A control register, CACON — 8-bit down counter with auto-reload function —...

  • Page 263: Counter A Block Diagram

    CADATAL register is loaded into the 8-bit counter. 12-2 16-Bit Down Counter Counter A Data Low Byte Register Counter A Data High Byte Register Data Bus Figure 12-1. Counter A Block Diagram CACON.0 To Other Block (CAOF) (P3.1/REM) CACON.3 IRQ2 INT. GEN. (CAINT) S3F80JB...

  • Page 264: Counter A Control Register (Cacon)

    S3F80JB COUNTER A CONTROL REGISTER (CACON) The counter A control register, CACON, is located in F3H, Set 1, Bank 0, and is read/write addressable. CACON contains control settings for the following functions (See Figure 12-2): — Counter A clock source selection —...

  • Page 265: Counter A Pulse Width Calculations

    = 24 us = (CADATAH + 2) / FX = (CADATAH + 2) x 1us, CADATAH = 22. 12-4 HIGH = 15 us. f = 4 MHz, FX = 4 MHz/4 = 1 MHz , and high period time, t S3F80JB HIGH.

  • Page 266: Counter A Output Flip-Flop Waveforms In Repeat Mode

    S3F80JB Counter A Clock CAOF = '0' CADATAL = 01-FFH CADATAH = 00H CAOF = '0' CADATAL = 00H CADATAH = 01-FFH CAOF = '0' CADATAL = 00H CADATAH = 00H CAOF = '1' CADATAL = 00H CADATAH = 00H...

  • Page 267: To Generate 38 Khz, 1/3Duty Signal Through P3.1

    ; Disable Counter A interrupt. ; Select repeat mode for Counter A. ; Start Counter A operation. ; Set Counter A Output Flip-flop(CAOF) high. ; Set P3.7(Carrier On/Off) to high. ; This command generates 38 kHz, 1/3duty pulse signal ; through P3.1 S3F80JB...

  • Page 268: To Generate A One Pulse Signal Through P3.1

    S3F80JB PROGRAMMING TIP — To generate a one-pulse signal through P3.1 This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source, and CADATAH and CADATAL to make a 40 µs width pulse. The program parameters are: —...

  • Page 269: Overview

    44 package; at the P3.0 for 32 package (You can select a rising edge, a falling edge, or both edges as the trigger). In the S3F80JB interrupt structure, the timer 2 overflow interrupt has higher priority than the timer 2 match or capture interrupt.

  • Page 270: Timer 2 Overflow Interrupt

    NOTE: P3.0 is assigned as T2CAP function for 32 pin package and P3.3 is assigned as T2CAP function for 42/44 pin package. Figure 13-1. Simplified Timer 2 Function Diagram: Capture Mode 13-2 16-Bit Up Counter Interrupt Enable/Disable (T2CON.1) Timer 2 Data T2CON.5 T2CON.4 T2CON.2 IRQ3 (T2OVF) Pending IRQ3 (T2INT) (T2CON.0) S3F80JB...

  • Page 271: Timer 2 Match Interrupt

    S3F80JB TIMER 2 MATCH INTERRUPT Timer 2 can also be used to generate a match interrupt (IRQ3, vector F2H) whenever the 16-bit counter value matches the value that is written to the timer 2 reference data registers, T2DATAH and T2DATAL. When a match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and up counting resumes from ‘00H’.

  • Page 272: Timer 2 Block Diagram

    16-Bit Compatator T2CON.5-.4 Timer 2 High/Low Buffer Register T1CON.3 Match Signal T2OVF Timer 2 Data High/Low Register Data Bus Match signal is occurrd only in interval mode. Figure 13-3. Timer 2 Block Diagram T2CON.2 IRQ3 T2CON.3 (note) T2CON.1 T1CON.0 IRQ3 S3F80JB...

  • Page 273: Timer 2 Control Register (T2Con)

    S3F80JB TIMER 2 CONTROL REGISTER (T2CON) The timer 2 control register, T2CON, is located in address E8H, Bank1, Set 1 and is read/write addressable. T2CON contains control settings for the following T2 functions: — Timer 2 input clock selection — Timer 2 operating mode selection —...

  • Page 274: Timer 2 Registers (T2Cnth, T2Cntl, T2Datah, T2Datal)

    E5H , Set 1, Bank 1, Read-only Timer 2 Data High-Byte Register (T2DATAH) E6H , Set 1, Bank 1, R/W Timer 2 Data Low-Byte Register (T2DATAL) E7H , Set 1, Bank 1, R/W Reset Value: 00H Reset Value: 00H Reset Value: FFH Reset Value: FFH S3F80JB...

  • Page 275: Overview

    S3F80JB COMPARATOR COMPARATOR OVERVIEW P2.4, P2.5, P2.6 and P2.7 can be used as analog input pins for a comparator. The reference voltage for the 4- channel comparator can be supplied either internally or externally at P2.7. When an internal reference voltage is used, four channels (P2.4–P2.7) are used for analog inputs and the internal reference voltage is varied in 16...

  • Page 276: Comparator Block Diagram For The S3F80Jb

    INT occurs only for digital input selecting. If an analog input, any INT doesn't occur. The comparison results of CIN0,CIN1,CIN2 and CIN3 are respectively stored in CMPREG0,CMPREG1,CMPREG2 and CMPREG3. Figure 14-1. Comparator Block Diagram for The S3F80JB 14-2 S3F80JB Internal BUS...

  • Page 277: Comparator Operation

    S3F80JB COMPARATOR OPERATION The comparator compares input analog voltage at CIN0–CIN3 with an external or internal reference voltage ) that is selected by the CMOD register. The result is written to the comparison result register CMPREG at address EAH, Set1, Bank1. The comparison result at internal reference is calculated as follows: Analog input voltage ≥...

  • Page 278: Comparator Mode Register (Cmod)

    Comparator Enale/Disable Bit 0:Comparator operation disable 1:Comparator operation enable Figure 14-3. Comparator Mode Register (CMOD) Comparator Input Selection Register (CMPSEL) Not used for S3F80JB. Figure 14-4. Comparator Input Selection Register (CMPSEL) 14-4 Not used for S3F80JB. Reference Voltage Selection Bits Selected Vref=Vdd x (N + 0.5)/16, n=0 to 15...

  • Page 279: Comparator Result Register (Cmpreg)

    S3F80JB COMPARATOR Comparator Result Register (CMPREG) EBH, Set1, Bank 1, R Not used for S3F80JB Comparator Result Data Figure 14-5. Comparator Result Register (CMPREG) 14-5...

  • Page 280: Overview

    EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F80JB has an on-chip flash memory internally instead of masked ROM. The flash memory is accessed by instruction ‘LDC’. This is a sector erasable and a byte programmable flash. User can program the data in a flash memory area any time you want.

  • Page 281: Descriptions Of Pins Used To Read/Write The Flash In Tool Program Mode

    This mode supports sector erase, byte programming, byte read and one protection mode (Hard Lock Protection). The S3F80JB has the internal pumping circuit to generate high voltage. Therefore, 12.5V into Vpp (TEST) pin is not needed. To program a flash memory in this mode several control registers will be used.

  • Page 282: Program Memory Address Space

    S3F80JB (ON-BOARD PROGRAMMING) SECTOR sectors located in program memory area can store On Board Program Software (Boot program code for upgrading application code by interfacing with I/O port pin). The ISP ‘LDC’ instruction for the safety of On Board Program Software.

  • Page 283: Smart Option

    Smart option is the program memory option for starting condition of the chip. The program memory addresses used by smart option are from 003CH to 003FH. The S3F80JB only use 003EH and 003FH. User can write any value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory is 0FFH (IPOR disable, LVD enable in the stop mode, Normal reset vector address 100H, ISP protection disable).

  • Page 284: Isp Reset Vector And Isp Sector Size

    S3F80JB 1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP area. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless. 2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H).

  • Page 285: Flash Memory Control Registers (User Program Mode)

    0101: Programming mode 1010: Erase mode 0110: Hard lock mode others: Not used for S3F80JB Figure 15-3. Flash Memory Control Register (FMCON) The bit 0 of FMCON register (FMCON.0) is a bit for the operation start of Erase and Hard Lock Protection.

  • Page 286: Flash Memory Sector Address Registers

    Address Sector Register High Byte) indicates the high byte of sector address. The FMSECH is needed for S3F80JB because it has 512 sectors. One sector consists of 128-bytes. Each sector’s address starts XX00H or XX80H, that is, a base address of sector is XX00H or XX80H.

  • Page 287: Sector Erase

    The program memory of S3F80JB, 64Kbytes flash memory, is divided into 512 sectors. Every sector has all 128- byte sizes. So the sector to be located destination address should be erased first to program a new data (one byte) into flash memory.

  • Page 288: Sector Erase Flowchart In User Program Mode

    In other words, when S3F80JB is in the condition that flash memory user programming enable bits is enabled and executes start operation of sector erase, it will get the result of erasing selected sector as user’s a purpose and Flash Operation Start Bit of FMCON register is also clear automatically.

  • Page 289: Sector Erase

    ; Selection the sector128 ( base address 4000H ) ; Set the sector range (m) to erase ; into High-byte(R6) and Low-byte(R7) SECTOR_ERASE P4,#11111111B ; Display ERASE_LOOP cycle SecNumH,R2 SecNumL,R3 R8,R6 R8,R7 R8,#00H NZ,ERASE_LOOP ; User program mode enable S3F80JB...
  • Page 290 S3F80JB SECTOR_ERASE: R12,SecNumH MULT MULT NOCARRY: ERASE_START: ERASE_STOP: FMUSR,#00H R14,SecNumL RR12,#80H ; Calculation the base address of a target sector RR14,#80H ; The size of one sector is 128-bytes R13,R14 ; BTJRF FLAGS.7,NOCARRY ; INC R10,R13 R11,R15 FMUSR,#0A5H ; User program mode enable FMSECH,R10 ;...

  • Page 291: Programming

    EMBEDDED FLASH MEMORY INTERFACE S3F80JB PROGRAMMING A flash memory is programmed in one-byte unit after sector erase. The write operation of programming starts by ‘LDC’ instruction. The program procedure in user program mode 1. Must erase target sectors before programming.

  • Page 292: Byte Program Flowchart In A User Program Mode

    S3F80JB Start FMSECH High Address of Sector FMSECL Low Address of Sector R(n) High Address to Write R(n+1) Low Address to Write R(data) 8-bit Data FMUSR FMCON @RR(n),R(data) FMUSR Finish 1-BYTE Writing Figure 15-9. Byte Program Flowchart in a User Program Mode ;...

  • Page 293: Program Flowchart In A User Program Mode

    Write again? FMUSR #00H ; Select Bank0 Finish Writing R(data) New 8-bit Data S3F80JB ; Select Bank1 ; Set Secotr Base Address ; Set Address and Data ; User Program Mode Enable ; Mode Select ; Write data at flash ;...

  • Page 294: Programming

    S3F80JB PROGRAMMING TIP — Programming Case1. 1-Byte Programming • • WR_BYTE: FMUSR,#0A5H FMCON,#01010000B FMSECH, #40H FMSECL, #00H R9,#0AAH R10,#40H R11,#10H @RR10,R9 FMUSR,#00H Case2. Programming in the same sector • • WR_INSECTOR: R0,#40H FMUSR,#0A5H FMCON,#01010000B FMSECH,#40H FMSECL,#00H R9,#33H R10,#40H R11,#40H WR_BYTE:...
  • Page 295 ; register ; Load flash memory lower address into lower register of pair working ; register ; Write data 'A3H' at flash memory location ; User Program mode disable ; Write data written by R9 at flash memory location S3F80JB...

  • Page 296: Reading

    S3F80JB READING The read operation starts by ‘LDC’ instruction. The program procedure in user program mode 1. Load a flash memory upper address into upper register of pair working register. 2. Load a flash memory lower address into lower register of pair working register.

  • Page 297: Hard Lock Protection

    Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”. PROGRAMMING TIP — Hard Lock Protection • • FMUSR,#0A5H FMCON,#01100001B FMUSR,#00H • • 15-18 ; User program mode enable ; Select Hard Lock Mode and Start protection ; User program mode disable S3F80JB...
  • Page 298 After power-on, LVD block is always enabled. LVD block is only disable when executed STOP instruction with a smart option setting. The LVD block of S3F80JB consists of two comparators and a resistor string. One of comparators is for LVD detection, and the other is for LVD_FLAG detection.
  • Page 299 4MHz operating frequency, the voltage gap between LVD and LVD_ FLAG is 250mV. IPOR/LVD Control Bit (smart option[7]@03FH) STOP Figure 16-1. Low Voltage Detect (LVD) Block Diagram 16-2 NOTES Resistor String Comparator DIV_Flag Comparator Bias BANDGAP S3F80JB (BackupMode /Reset) Bias LVDCON.0 (LVD Flag Bit)

  • Page 300: Low Voltage Detector Control Register (Lvdcon)

    S3F80JB LOW VOLTAGE DETECTOR CONTROL REGISTER (LVDCON) LVDCON.0 is used flag bit to indicate low battery in IR application or others. When LVD circuit detects LVD_FLAG, LVDCON.0 flag bit is set automatically. The reset value of LVDCON is #00H. Low Voltage Detect Control Register (LVDCON) NOTE: Figure 16-2.

  • Page 301: Overview

    S3F80JB ELECTRICAL DATA (4MHz) ELECTRICAL DATA – 4MHz OVERVIEW In this section, S3F80JB electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute Maximum Ratings — D.C. Electrical Characteristics — Characteristics of Low Voltage Detect Circuit —...
  • Page 302 – 60 + 30 + 150 – 25 to + 85 – 65 to + 150 2000 – 0.8 V – 0.85 V – 0.3 0.2 V – 0.2 V – 1.0 – – – – S3F80JB Unit °C °C Unit...
  • Page 303 S3F80JB Table 17-2. D.C. Electrical Characteristics (Continued) = – 25 °C to + 85 °C, V Parameter Symbol Output Low Voltage Input High LIH1 Leakage Current LIH2 Input Low LIL1 Leakage Current LIL2 Output High Leakage Current Output Low Leakage Current...
  • Page 304 LVD ON, V = 3.6 V Symbol Conditions ∆V – – LVD_FLAG – Symbol Conditions – DDDR = 1.5 V DDDR DDDR Stop Mode – – – – – 1.95 2.15 2.35 – – – S3F80JB Unit Unit Unit µA...

  • Page 305: Typical Low-Side Driver (Sink) Characteristics (P3.0 And P2.0-2.3) ·························

    S3F80JB TYPICAL VOL vs IOL(VDD=3.3V) 1.00 85°C 25°C 0.80 −25°C 0.60 0.40 0.20 0.00 IOL(mA) Figure 17-1. Typical Low-Side Driver (Sink) Characteristics (P3.1 only) TYPICAL VOL vs IOL(VDD=3.3V) 1.00 85°C 25°C 0.80 −25°C 0.60 0.40 0.20 0.00 IOL(mA) Figure 17-2. Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3) NOTE: Figure 17-1 and 17-2 are characterized and not tested on each device.

  • Page 306: Port0, Port1, P2.4-2.7, P3.4-P3.5 And Port4) ··························································

    Figure 17-4. Typical High-Side Driver (Source) Characteristics (P3.1 only) NOTE: Figure 17-3 and 17-4 are characterized and not tested on each device. 17-6 1.800V 1.8V TYPICAL VOL VS VDD(IOL=2mA) 2.400V 3.000V 3.600V VDD(V) TYPICAL VDD-VOH VS VDD(IOH=−6mA) VDD(V) S3F80JB 85°C 25°C −25°C 85°C 25°C −25°C 3.8V...

  • Page 307: Port0, Port1, P2.4-2.7, P3.4-P3.5 And Port4) ··························································

    S3F80JB TYPICAL VDD-VOH(VDD=3.3V) 1.20 85°C 25°C 1.00 −25°C 0.80 0.60 0.40 0.20 0.00 IOH(mA) Figure 17-5. Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3) TYPICAL VDD-VOH(VDD=3.3V) 1.20 85°C 25°C 1.00 −25°C 0.80 0.60 0.40 0.20 0.00 IOH(mA) Figure 17-6. Typical High-Side Driver (Source) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) NOTE: Figure 17-5 and 17-6 are characterized and not tested on each device.

  • Page 308: Stop Mode Release Timing When Initiated By An External Interrupt·························

    Figure 17-8. Stop Mode Release Timing When Initiated by a Reset 17-8 Stop Mode Data Retention Mode DDDR 0.2V Reset Occur Stop Mode 0.2V Idle Mode (Basic Timer Active) Normal Operating Mode 0.8V WAIT Oscillation Stabilization Time Normal Operating Mode 0.85V WAIT S3F80JB...

  • Page 309: Stop Mode Release Timing When Initiated By A Lvd ···············································

    S3F80JB Execution of STOP Instrction NOTE: is the same as 4096 x 16 x 1/f WAIT Figure 17-9. Stop Mode Release Timing When Initiated by a LVD = – 25 °C to + 85 °C) Parameter Symbol Input Capacitance Output...

  • Page 310: Input Timing For Reset (Nreset Pin)·······································································

    4096 x 16 x 1/f WAIT Figure 17-11. Input Timing for Reset (nRESET Pin) 17-10 INTL 0.8 V 0.2 V means one CPU clock period. Back-up Mode (Stop Mode) INTH 0.8 V Reset Oscillation Stabilization Time Occur Normal Operating Mode WAIT S3F80JB...
  • Page 311 S3F80JB = – 25 °C to + 85 °C) Oscillator Clock Circuit Crystal Ceramic External Clock External Clock Open Pin Table 17-7. Oscillation Characteristics Conditions CPU clock oscillation frequency CPU clock oscillation frequency input frequency ELECTRICAL DATA (4MHz) Unit –...
  • Page 312 BTCON. 17-12 Table 17-8. Oscillation Stabilization Time Test Condition ) when it is released by an interrupt is determined by the setting in WAIT – – – – – – – – – – S3F80JB Unit...
  • Page 313 S3F80JB Minimun Instruction Clock 2 MHz 1.5MHz 1MHz 500 kHz 250 kHz 1kHz Minimun Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, or 16) A: 1.7 V, 4 MHz Figure 17-12. Operating Voltage Range of S3F80J9 Table 17-9.
  • Page 314 S3F80JB ELECTRICAL DATA (8MHz) ELECTRICAL DATA – 8MHZ OVERVIEW In this section, S3F80JB electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute Maximum Ratings — D.C. Electrical Characteristics — Characteristics of Low Voltage Detect Circuit —...
  • Page 315 + 30 + 150 – 25 to + 85 – 65 to + 150 2000 1.95 – 0.8 V – 0.85 V – 0.3 0.2 V – 0.2 V – 0.7 – – – – S3F80JB Unit °C °C Unit...
  • Page 316 S3F80JB Table 18-2. D.C. Electrical Characteristics (Continued) = – 25 °C to + 85 °C, V Parameter Symbol Output Low Voltage Input High LIH1 Leakage Current LIH2 Input Low LIL1 Leakage Current LIL2 Output High Leakage Current Output Low Leakage Current...
  • Page 317 LVD ON, V = 3.6 V Symbol Conditions ∆V – – LVD_FLAG – Symbol Conditions – DDDR = 1.5 V DDDR DDDR Stop Mode – – – – – 1.95 2.15 2.35 – – – S3F80JB Unit Unit Unit µA...
  • Page 318 S3F80JB TYPICAL VOL vs IOL(VDD=3.3V) 1.00 85°C 25°C 0.80 −25°C 0.60 0.40 0.20 0.00 IOL(mA) Figure 18-1. Typical Low-Side Driver (Sink) Characteristics (P3.1 only) TYPICAL VOL vs IOL(VDD=3.3V) 1.00 85°C 25°C 0.80 −25°C 0.60 0.40 0.20 0.00 IOL(mA) Figure 18-2. Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3) NOTE: Figure 18-1 and 18-2 are characterized and not tested on each device.
  • Page 319 Figure 18-4. Typical High-Side Driver (Source) Characteristics (P3.1 only) NOTE: Figure 18-3 and 18-4 are characterized and not tested on each device. 18-6 1.800V TYPICAL VDD-VOH VS VDD(IOH=−6mA) 1.8V TYPICAL VOL VS VDD(IOL=12mA) 2.400V 3.000V 3.600V VDD(V) VDD(V) S3F80JB 85°C 25°C −25°C 85°C 25°C −25°C 3.8V...
  • Page 320 S3F80JB TYPICAL VDD-VOH(VDD=3.3V) 25 °C 1.20 85°C -25 °C 25°C 1.00 −25°C 0.80 0.60 0.40 0.20 0.00 IOH(mA) Figure 18-5. Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3) TYPICAL VDD-VOH(VDD=3.3V) 1.20 85°C 25°C 1.00 −25°C 0.80 0.60 0.40 0.20 0.00 IOH(mA) Figure 18-6.
  • Page 321 Figure 18-8. Stop Mode Release Timing When Initiated by a Reset 18-8 Stop Mode Data Retention Mode DDDR 0.2V Reset Occur Stop Mode 0.2V Idle Mode (Basic Timer Active) Normal Operating Mode 0.8V WAIT Oscillation Stabilization Time Normal Operating Mode 0.85V WAIT S3F80JB...
  • Page 322 S3F80JB Execution of STOP Instrction NOTE: is the same as 4096 x 16 x 1/f WAIT Figure 18-9. Stop Mode Release Timing When Initiated by a LVD = – 25 °C to + 85 °C) Parameter Symbol Input Capacitance Output...
  • Page 323 4096 x 16 x 1/f WAIT Figure 18-11. Input Timing for Reset (nRESET Pin) 18-10 INTL 0.8 V 0.2 V means one CPU clock period. Back-up Mode (Stop Mode) INTH 0.8 V Reset Oscillation Stabilization Time Occur Normal Operating Mode WAIT S3F80JB...
  • Page 324 S3F80JB Table 18-7. Comparator Electrical Characteristics ° ° = –25 C to + 85 C, V = 1.95 V to 3.6 V, V Parameter Input voltage range Reference voltage range Input voltage Internal Accuracy External Input leakage current = –25 °C to + 85 °C)
  • Page 325 BTCON. 18-12 Table 18-9. Oscillation Stabilization Time Test Condition ) when it is released by an interrupt is determined by the setting in WAIT – – – – – – – – – – S3F80JB Unit...
  • Page 326 The programming time is the time during which one byte (8-bit) is programmed. The Sector erasing time is the time during which all 128-bytes of one sector block is erased. In the case of S3F80JB, the chip erasing is available in Tool Program Mode only. Supply Voltage (V)
  • Page 327 ELECTRICAL DATA (8MHz) S3F80JB NOTES 18-14...

  • Page 328: Pin Sop Package Dimension

    S3F80JB MECHANICAL DATA OVERVIEW The S3F80JB microcontroller is currently available in a 32-pin SOP and 44-pin QFP package. (0.43) NOTE: Dimensions are in millimeters. 32-SOP-450A 20.30 MAX ± 0.20 19.90 0.40 ± 0.10 1.27 Figure 19-1. 32-Pin SOP Package Dimension MECHANICAL DATA + 0.10...

  • Page 329: Pin Qfp Package Dimension

    NOTE: Dimensions are in millimeters. 19-2 ± 0.30 13.20 ± 0.20 10.00 44-QFP-1010B + 0.10 0.35 - 0.05 0.80 (1.00) 0.15 MAX Figure 19-2. 44-Pin QFP Package Dimension S3F80JB + 0.10 0.15 - 0.05 0.10 MAX 0.05 MIN ± 0.10 2.05 2.30 MAX...

  • Page 330: Target Boards

    TARGET BOARDS Target boards are available for all the S3C8/S3F8-series microcontrollers. All the required target system cables and adapters are included on the device-specific target board. TB80JB is a specific target board for the S3F80JB development. PROGRAMMING SOCKET ADAPTER When you program S3F80JB’s flash memory by using an emulator or OTP/MTP writer, you need a specific writer...

  • Page 331: Tb80Jb Target Board

    DEVELOPMENT TOOLS DATA TB80JB TARGET BOARD The TB80JB target board is used for the S3F80JB microcontrollers. It is supported by OPENice-i500 (In-Circuit Emulator). CABLEs For CONNECTION To Open-ice500 TA-SAM 8 Figure 20-1. TB80JB Target Board Configuration 1. S3E80JB should be supplied 3.3V. So jumpers and switches in both OPENice-i500 connect board and target board of S3E80JB (TB80JB) should be set as like this description.
  • Page 332 S3F80JB Table 20-1. Components Consisting of S3F80JB Target Board Block OPEN-i500 Connector TEST Board Connector RESET Block RESET Push Switch POWER Block VCC, GND, S, nRESET LED STOP/IDLE Display IDLE, STOP LED FLASH Serial Writing MODE Selection JP1, JP2 Symbols Connection debugging signals between emulator and 80JB EVA target board.
  • Page 333 NOTE: S3F80JB Target board consists of 74HC11N, regulator and other components. In case of 74HC11N, typical operating voltage is 5V. So 80jb target board includes a regulator for 3.3V generation. As you know, S3F80JB typical operating voltage is 3.3V. Although open-i500 supports 3.3 V for target board ‘s power source, we recommend that you connect jumper of open-i500 power source to 5V.

  • Page 334: Pin Connector Pin Assignment For Tb80Jb ·························································

    S3F80JB P3.0/T0PWM/T0CAP/SDAT Figure 20-2. 50-Pin Connector Pin Assignment for TB80JB Target Board Figure 20-3. TB80JB Adapter Cable for 44-QFP Package J2 (for 44-QFP) P2.3/INT8 P2.4/INT9/CIN0 P3.1/REM/SCLK TEST P2.5/INT9/CIN1 P2.6/INT9/CIN2 RESET P3.4 P3.5 P2.7/INT9/CIN3 P1.0 P3.2/T0CK P3.3/T1CAP/T2CAP P4.7 P1.1 P1.2 P1.3 NOTE: N.C means No Connection.
  • Page 335 SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG In- circuit emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with an OTP/MTP programmer.

  • Page 336: Otp/Mtp Programmer (Writer)

    BlueChips-Combi BlueChips-combi is a programmer for all Samsung MCU. It can program not only all Samsung OTP/MTP (Flash) MCU but also the popular E(E)PROMs. New devices will be supported just by adding device files or upgrading the software. It is connected to host PC’s serial port and controlled by...
  • Page 337 New product Replacement of an existing product If you are replacing an existing product, please indicate the former product name What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price...
  • Page 338 _______________________________ (Person Placing the Risk Order) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3F8 SERIES REQUEST Quantity...
  • Page 339 FLASH APPLICATION NOTES S3F80JB Programming By Tool...
  • Page 340 When writing or erasing using OTP/MTP writer, user must check the following: — Vdd Voltage The maximum operating voltage of S3F80JB is 3.6V. (Refer to the electrical data of S3F80JB manual.) The selection flag of Vdd must be set to 3.3V as like a figure on next page.
  • Page 341 S3F80JB This is only an example for setting Vdd. This is SPW2+ which is one of OPT/MTP Writers.

  • Page 342: Important Note

    Important Note Subject : Toggling phenomenon when serial writing programming on the S3F80JB.
  • Page 343 Important Note S3F80JB 1. ANALYSIS RESULT When serial writing programming on S3F80JB, only port1.4,1.5,1.6,1.7 are affected by SDAT signal. This phenomenon is only port1.4,1.5,1.6,1.7 issues and in normal operating mode it never be occurred. 2. ANALYSIS OF PHENOMENON 2.1 FOR SERIAL PROGRAMMING MODE The S3F80JB/9 is needed to nRESET pin = “0(GND)”...
  • Page 344 S3F80JB Important Note 2.2 FOR NORMAL OPERATING MODE The S3F80JB/9 is needed to nRESET pin = “1(VDD)” & TEST pin = “0(GND)” P1.4~1.7 When nRESET pin = “1(VDD)” & TEST pin = “0(GND)” In the Figure 2, because TEST signal is low(Logic level 0), “outdis” and “data” signal is same to MUX “0” signal.
  • Page 345 3. DIFFERENCE S3F80JB AND S3F80J9 3.1 WHEN TEST PIN = “1(VDD)” This is Fabrication Test mode (For Design team & PE ) : Design team & PE team tested S3F80JB by using When S3F80JB Port1.0~1.7 is used to address & data port between Advan equipment and S3F80JB. When Advan equipment sends data to S3F80JB, port1.0~1.7 is input mode.
  • Page 346 S3F80JB Important Note When S3F80J9 On S3F80J9, address & data port is different from S3F80JB. Because the 28-SOP type doesn’t have port1.4~1.7, port1.0~1.3 and port2.4~2.7 are used to address & data port. (S3F80J9 is supported to 32-SOP and 28-SOP type.) 4.

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