Samsung S3C2451X User Manual page 147

S3C2451X RISC MICROPROCESSOR
Mobile DRAM Refresh CONTROL REGISTER
Register
REFRESH
REFRESH Bit
Reserved [31:16]
REFCYC [15:0]
MOBILE DRAM WRITE BUFFER TIME OUT REGISTER
A write to a enabling write buffer loads the value in the timeout register into timeout down counter of the buffer.
When the timeout counter reached 0 the contents of write buffer is flushed to the external DRAM. The down
counter is clocked HCLK. Writing a value of 0 in the TIMEOUT register disables the write buffer timeout function.
Register
TIMEOUT
TIMEOUT Bit
Reserved [31:16]
TIMEOUT [15:0]
Address R/W
0x48000010 R/W
Reserved
DRAM refresh cycle.
Example: Refresh period is 15.6us, and HCLK is 66MHz. The
value of REFCYC is as follows:
REFCYC = 15.6 x 10
Address R/W
0x48000014 R/W
Reserved
Write buffer time-out delay time
Description
Mobile DRAM refresh control register
Description
-6 6
x 66 x 10 = 1029
Description
Write Buffer Time out control register
Description
MOBILE DRAM CONTROLLER
Reset Value
0x0000_0020
Initial State
0x0000
0x0020
Reset Value
0x0000_0000
Initial State
0x0000
0x0000
6-15