Samsung S3C2451X User Manual page 599

S3C2451X RISC MICROPROCESSOR
CLOCK DOMAIN
CAMIF has two clock domains. The one is the system bus clock, which is HCLK. The other is the pixel clock,
which is PCLK. The system clock must be faster than pixel clock. As shown in figure 23-8, CAMCLK must be
divided from the fixed frequency like USB PLL clock. If external clock oscillator were used, CAMCLK should be
floated. Internal scaler clock is system clock. It is not necessary for two clock domains to be synchronized each
other. Other signals as PCLK should be similarly connected to shimitt-triggered level shifter.
f /d or HCLK/d
EPLL
Normally use
External
Camera
Processor
FRAME MEMORY HIRERARCHY
Frame memories consist of four ping-pong memories for each P- and C-ports. C-port ping-pong memories have
three element memories that are luminance Y, chrominance Cb, and chrominance Cr. It is recommended that the
arbitration priority of CAMIF must be higher than any other masters except LCD controller. It is strongly
recommended that CAMIF priorities should be the fixed priorities, not rotation priorities. And in multi-AHB bus
case, the priority of system bus including CAMIF must be higher than others. If AHB-bus is traffic enough that
DMA operation is not ending during one horizontal period plus blank, it might be entered into mal-function. So, the
priority of CAMIF must be separated to other round robin or circular arbitration priorities. Also, it is recommended
that AHB bus which include CAMIF, should have higher priority than any other multi-AHB buses in memory matrix
system. And CAMIF should not be the default master of AMBA AHB system.
CAMCLK
PCLK
Figure 23-8. CAMIF clock generation
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
EPLL/
EPLL(96 MHz)
HCLK
or HCLK
HCLK
/ f
EPLL
1/1, 1/2, 1/3 . . . ~
Divide
1/16
Counter
CAMIF
CAMERA INTERFACE
Variable
Freq.
MPLL
f
Empll
Divide
Counter
f /d
mpll
HCLK
23-7