Samsung S3C2451X User Manual page 218

DMA CONTROLLER
DMA INITIAL DESTINATION REGISTER (DIDST)
Register
DIDST0 0x4B000008
DIDST1 0x4B000108
DIDST2 0x4B000208
DIDST3 0x4B000308
DIDST4 0x4B000408
DIDST5 0x4B000508
DIDST6 0x4B000608
DIDST7 0x4B000708
DIDSTn Bit
D_ADDR [30:0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
9-10
Specifications and information herein are subject to change without notice.
Address R/W
R/W DMA0 Initial Destination Register
R/W DMA1 Initial Destination Register
R/W DMA2 Initial Destination Register
R/W DMA3 Initial Destination Register
R/W DMA4 Initial Destination Register
R/W DMA5 Initial Destination Register
R/W DMA6 Initial Destination Register
R/W DMA7 Initial Destination Register
These bits are the base address (start address) of destination for
the transfer. This value will be loaded into CURR_SRC only if the
CURR_SRC is 0 and the DMA ACK is 1.
S3C2451X RISC MICROPROCESSOR
Description
Description
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Initial State
0x00000000