Samsung S3C2451X User Manual page 609

S3C2451X RISC MICROPROCESSOR
GLOBAL CONTROL REGISTER
Register
CIGCTRL 0x4D80_0008
CIGCTRL Bit
[31]
SwRst
CamRst [30]
Reserved [29]
[28:27]
TestPattern
InvPolPCLK [26]
InvPolVSYNC [25]
InvPolHREF [24]
Non-use [23]
[22]
IRQ_Ovfen
[21]
Href_mask
Reserved [20:0]
FIELDMODE
InvPolFIELD
Cam_Interlace
Address R/W
RW
Camera interface software reset. Before setting this bit, you
should set the ITU601_656n bit of CISRCFMT as "1"
temporarily at first SFR setting. Next sequence is
recommended.
(ITU601 case : ITU601_656n "1" → SwRst "1" → SwRst "0"
for first SFR setting ,
ITU656 case : ITU601_656n "1" → SwRst "1" → SwRst "0"
→ ITU601_656n "0" for first SFR setting)
External camera processor Reset or Power Down control
Must be 1
This register should be set at only ITU-T 601 8-bit mode. Not
allowed with ITU-T 656 mode. (max. 1280 X 1024)
00 : external camera processor input (normal)
01 : color bar test pattern
10 : horizontal increment test pattern
11 . vertical increment test pattern
1 : inverse the polarity of PCLK
1 : inverse the polarity of VSYNC
1 : inverse the polarity of HREF
1 : Overflow interrupt enable (Interrupt is generated during
overflow occurrence)
0 : Overflow interrupt disable (normal)
1 : mask out Href during Vsync high
0 : no mask
ITU601 Interlace field port mode enable (don't care this bit in
[2] itu656). This bit should be connected with FIELD signal
1 : FIELD port enable
[1] 1 : inverse the polarity of FIELD
External camera data transmission mode
[0]
1 : Interlace 0 : Progressive
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Global control register
Description
0 : normal
0 : normal
0 : normal
0: disable
0 : normal
CAMERA INTERFACE
Reset Value
2000_0000
Initial Change
State State
0 X
0 X
1 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
23-17