Samsung S3C2451X User Manual page 383

S3C2451X RISC MICROPROCESSOR
TEST REGISTER (TR)
The test register is used for the diagnostics. All bit are activated when 1 is written to and is cleared by 0 on them.
Bit[3:0] are for the high speed device only.
Register Address
TR 0x4980_0018
TR Bit
[31:5]
TMD [4]
TPS [3]
TKS [2]
TJS [1]
TSNS [0]
R/W
R/W Test Register
R/W
Reserved
R/W Test Mode.
When TMD is set to 1. The core is forced into the test mode.
Following TPS, TKS, TJS, TSNS bits are meaningful in test
mode.
R/W Test Packets.
If this bit is set, the USB repetitively transmit the test
packets to Host.
The test packets are explained in 7.1.20 of USB 2.0
specification.
This bit can be set when TMD bit is set.
R/W Test K Select.
If this bit is set, the transceiver port enters into the high-
speed K state.
This bit can be set when TMD bit is set.
R/W Test J Select.
If this bit is set, the transceiver port enters into the high-
speed J state.
This bit can be set when TMD bit is set.
R/W Test SE0 NAK Select
If this bit is set, the transceiver enters into the high speed
receive mode and must respond to any IN token with NAK
handshake.
This bit can be set when TMD bit is set.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
USB2.0 DEVICE
Reset Value
0x0
Initial State
0
0
0
0
0
17-11