Samsung S3C2451X User Manual page 91

S3C2451X RISC MICROPROCESSOR
The CLKSRC selects the source input of the clocks.
CLKSRC Bit
RESERVED [31:21]
SEL_CAMCLK [20]
SELHSSPI1 [19]
SELHSSPI0 [18]
SELHSMMC1 [17]
SELHSMMC0 [16]
SELI2S [15:14]
SELI2S_1 [13:12]
RESERVED [11:9]
SELESRC [8:7]
SELEPLL [6]
RESERVED
[4]
SELMPLL
SELEXTCLK [3]
RESERVED [2:0]
-
Source clock of CAMCLK divider
0 = EPLL, 1 = HCLK
HS-SPI0 clock
0 = EPLL (divided), 1 = MPLL (divided)
HS-SPI0 clock
0 = EPLL (divided), 1 = MPLL (divided)
HSMMC1 clock
0 = EPLL (divided), 1 = EXTCLK
HSMMC0 clock
0 = EPLL (divided), 1 = EXTCLK
I2S clock source selection
00 = divided clock of EPLL, 01 = external I2S clock
1X = EpllRefClk
I2S_1 clock source selection
00 = divided clock of EPLL, 01 = external I2S clock
1X = EpllRefClk
-
Selection EPLL reference clock
10 = XTAL, 11 = EXTCLK
0x = identical to that of MPLL reference clock
Do not configure SELESRC & SELEPLL register simultaneously.
EsysClk selection
0 = EPLL reference clock, 1 = EPLL output
[5] -
MSYSCLK selection
0 = MPLL reference clock (produced through clock divider)
1 = MPLL output
Configure MPLL reference clock divider
0 = don't use MPLL reference clock divider (means 1/1 divide
ratio)
1 = use MPLL reference clock divider (See EXTDIV field of
CLKDIV)
-
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
SYSTEM CONTROLLER
Initial Value
0x0_0000
0
0
0
0
0
0x0
0x0
0
00
0
0
0
0
0x0
2-25